[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.

It may not be perfect yet but the SB1 code is badly borken and has
horrible performance issues.

Downside: This seriously breaks support for pass 1 parts of the BCM1250
where indexed cacheops don't work quite reliable but I seem to be the
last one on the planet with a pass 1 part anyway.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 1 insertions, 1 deletions

diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 43e4810dcaa8..32fd5db95774 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R5432)		+= c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
 obj-$(CONFIG_CPU_R8000)         += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o
 obj-$(CONFIG_CPU_RM7000)        += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
 obj-$(CONFIG_CPU_RM9000)        += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
-obj-$(CONFIG_CPU_SB1)           += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \
+obj-$(CONFIG_CPU_SB1)           += c-r4k.o cerr-sb1.o cex-sb1.o pg-sb1.o \
                                    tlb-r4k.o
 obj-$(CONFIG_CPU_TX39XX)        += c-tx39.o pg-r4k.o tlb-r3k.o
 obj-$(CONFIG_CPU_TX49XX)        += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o