diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2009-06-19 10:01:44 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2009-06-24 13:34:39 -0400 |
| commit | 44eeab67416711db9b84610ef18c99a60415dff8 (patch) | |
| tree | e9beb9000be5cd9c17bbb7bc05cd3db1c4cb3f09 /arch/mips/mipssim | |
| parent | 631330f5847b3f8a7ea67d689e9f7c56833ccaa6 (diff) | |
MIPS: Hibernation: Remove SMP TLB and cacheflushing code.
We can't perform any flushes on SMP from swsusp_arch_resume because
interrupts are disabled. A cross-CPU flush is unnecessary anyway
because all but the local CPU have already been disabled. A local
flush is not needed either because we didn't change any mappings. So
just delete the code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mipssim')
0 files changed, 0 insertions, 0 deletions