diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-29 10:23:43 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-29 15:35:36 -0400 |
commit | 38760d40ca61b18b2809e9c28df8b3ff9af8a02b (patch) | |
tree | dd65b99f1ae919498808506121a2b75217997713 /arch/mips/mipssim | |
parent | 1238d5d868a56dcbc743d3ffc9bd3c920258b4cb (diff) |
[MIPS] time: Replace plat_timer_setup with modern APIs.
plat_timer_setup is no longer getting called.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mipssim')
-rw-r--r-- | arch/mips/mipssim/sim_time.c | 52 |
1 files changed, 22 insertions, 30 deletions
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c index e7fa0d1078a3..bfaafa38846f 100644 --- a/arch/mips/mipssim/sim_time.c +++ b/arch/mips/mipssim/sim_time.c | |||
@@ -75,25 +75,6 @@ static unsigned int __init estimate_cpu_frequency(void) | |||
75 | return count; | 75 | return count; |
76 | } | 76 | } |
77 | 77 | ||
78 | void __init plat_time_init(void) | ||
79 | { | ||
80 | unsigned int est_freq, flags; | ||
81 | |||
82 | local_irq_save(flags); | ||
83 | |||
84 | /* Set Data mode - binary. */ | ||
85 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); | ||
86 | |||
87 | est_freq = estimate_cpu_frequency(); | ||
88 | |||
89 | printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, | ||
90 | (est_freq % 1000000) * 100 / 1000000); | ||
91 | |||
92 | cpu_khz = est_freq / 1000; | ||
93 | |||
94 | local_irq_restore(flags); | ||
95 | } | ||
96 | |||
97 | static int mips_cpu_timer_irq; | 78 | static int mips_cpu_timer_irq; |
98 | 79 | ||
99 | static void mips_timer_dispatch(void) | 80 | static void mips_timer_dispatch(void) |
@@ -102,26 +83,37 @@ static void mips_timer_dispatch(void) | |||
102 | } | 83 | } |
103 | 84 | ||
104 | 85 | ||
105 | void __init plat_timer_setup(struct irqaction *irq) | 86 | unsigned __init get_c0_compare_int(void) |
106 | { | 87 | { |
88 | #ifdef MSC01E_INT_BASE | ||
107 | if (cpu_has_veic) { | 89 | if (cpu_has_veic) { |
108 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); | 90 | set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch); |
109 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; | 91 | mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; |
110 | } else { | 92 | } else { |
93 | #endif | ||
111 | if (cpu_has_vint) | 94 | if (cpu_has_vint) |
112 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); | 95 | set_vi_handler(cp0_compare_irq, mips_timer_dispatch); |
113 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; | 96 | mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; |
114 | } | 97 | } |
115 | 98 | ||
116 | /* we are using the cpu counter for timer interrupts */ | 99 | return mips_cpu_timer_irq; |
117 | setup_irq(mips_cpu_timer_irq, irq); | 100 | } |
118 | 101 | ||
119 | #ifdef CONFIG_SMP | 102 | void __init plat_time_init(void) |
120 | /* irq_desc(riptor) is a global resource, when the interrupt overlaps | 103 | { |
121 | on seperate cpu's the first one tries to handle the second interrupt. | 104 | unsigned int est_freq, flags; |
122 | The effect is that the int remains disabled on the second cpu. | 105 | |
123 | Mark the interrupt with IRQ_PER_CPU to avoid any confusion */ | 106 | local_irq_save(flags); |
124 | irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; | 107 | |
125 | set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); | 108 | /* Set Data mode - binary. */ |
126 | #endif | 109 | CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); |
110 | |||
111 | est_freq = estimate_cpu_frequency(); | ||
112 | |||
113 | printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, | ||
114 | (est_freq % 1000000) * 100 / 1000000); | ||
115 | |||
116 | cpu_khz = est_freq / 1000; | ||
117 | |||
118 | local_irq_restore(flags); | ||
127 | } | 119 | } |