[MIPS] Add support for MIPS CMP platform.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

7 files changed, 461 insertions, 5 deletions

diff --git a/arch/mips/mips-boards/generic/Makefile b/arch/mips/mips-boards/generic/Makefile
index b31d8dfed1be..f7f87fc09d1e 100644
--- a/arch/mips/mips-boards/generic/Makefile
+++ b/arch/mips/mips-boards/generic/Makefile
@@ -20,6 +20,7 @@
 
 obj-y                           := reset.o display.o init.o memory.o \
                                    cmdline.o time.o
+obj-y                           += amon.o
 
 obj-$(CONFIG_EARLY_PRINTK)      += console.o
 obj-$(CONFIG_PCI)               += pci.o
diff --git a/arch/mips/mips-boards/generic/amon.c b/arch/mips/mips-boards/generic/amon.c
new file mode 100644
index 000000000000..b7633fda4180
--- /dev/null
+++ b/arch/mips/mips-boards/generic/amon.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2007  MIPS Technologies, Inc.
+ *      All rights reserved.
+
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Arbitrary Monitor interface
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+
+#include <asm-mips/addrspace.h>
+#include <asm-mips/mips-boards/launch.h>
+#include <asm-mips/mipsmtregs.h>
+
+int amon_cpu_avail(int cpu)
+{
+        struct cpulaunch *launch = (struct cpulaunch *)KSEG0ADDR(CPULAUNCH);
+
+        if (cpu < 0 || cpu >= NCPULAUNCH) {
+                pr_debug("avail: cpu%d is out of range\n", cpu);
+                return 0;
+        }
+
+        launch += cpu;
+        if (!(launch->flags & LAUNCH_FREADY)) {
+                pr_debug("avail: cpu%d is not ready\n", cpu);
+                return 0;
+        }
+        if (launch->flags & (LAUNCH_FGO|LAUNCH_FGONE)) {
+                pr_debug("avail: too late.. cpu%d is already gone\n", cpu);
+                return 0;
+        }
+
+        return 1;
+}
+
+void amon_cpu_start(int cpu,
+                    unsigned long pc, unsigned long sp,
+                    unsigned long gp, unsigned long a0)
+{
+        volatile struct cpulaunch *launch =
+                (struct cpulaunch  *)KSEG0ADDR(CPULAUNCH);
+
+        if (!amon_cpu_avail(cpu))
+                return;
+        if (cpu == smp_processor_id()) {
+                pr_debug("launch: I am cpu%d!\n", cpu);
+                return;
+        }
+        launch += cpu;
+
+        pr_debug("launch: starting cpu%d\n", cpu);
+
+        launch->pc = pc;
+        launch->gp = gp;
+        launch->sp = sp;
+        launch->a0 = a0;
+
+        /* Make sure target sees parameters before the go bit */
+        smp_mb();
+
+        launch->flags |= LAUNCH_FGO;
+        while ((launch->flags & LAUNCH_FGONE) == 0)
+                ;
+        pr_debug("launch: cpu%d gone!\n", cpu);
+}
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index 07671fb9074f..852b19492d8c 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -424,6 +424,9 @@ void __init prom_init(void)
 #ifdef CONFIG_SERIAL_8250_CONSOLE
         console_config();
 #endif
+#ifdef CONFIG_MIPS_CMP
+        register_smp_ops(&cmp_smp_ops);
+#endif
 #ifdef CONFIG_MIPS_MT_SMP
         register_smp_ops(&vsmp_smp_ops);
 #endif
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index b50e0fc406ac..4fe62fca994e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -55,16 +55,36 @@
 unsigned long cpu_khz;
 
 static int mips_cpu_timer_irq;
+static int mips_cpu_perf_irq;
 extern int cp0_perfcount_irq;
 
+DEFINE_PER_CPU(unsigned int, tickcount);
+#define tickcount_this_cpu __get_cpu_var(tickcount)
+static unsigned long ledbitmask;
+
 static void mips_timer_dispatch(void)
 {
+#if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS)
+        /*
+         * Yes, this is very tacky, won't work as expected with SMTC and
+         * dyntick will break it,
+         * but it gives me a nice warm feeling during debug
+         */
+#define LEDBAR 0xbf000408
+        if (tickcount_this_cpu++ >= HZ) {
+                tickcount_this_cpu = 0;
+                change_bit(smp_processor_id(), &ledbitmask);
+                smp_wmb(); /* Make sure every one else sees the change */
+                /* This will pick up any recent changes made by other CPU's */
+                *(unsigned int *)LEDBAR = ledbitmask;
+        }
+#endif
         do_IRQ(mips_cpu_timer_irq);
 }
 
 static void mips_perf_dispatch(void)
 {
-        do_IRQ(cp0_perfcount_irq);
+        do_IRQ(mips_cpu_perf_irq);
 }
 
 /*
@@ -129,19 +149,18 @@ unsigned long read_persistent_clock(void)
 
 void __init plat_perf_setup(void)
 {
-        cp0_perfcount_irq = -1;
-
 #ifdef MSC01E_INT_BASE
         if (cpu_has_veic) {
                 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
-                cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
+                mips_cpu_perf_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
         } else
 #endif
         if (cp0_perfcount_irq >= 0) {
                 if (cpu_has_vint)
                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
+                mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 #ifdef CONFIG_SMP
-                set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
+                set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
 #endif
         }
 }
diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile
index 931ca4600a63..8dc6e2ac4c03 100644
--- a/arch/mips/mips-boards/malta/Makefile
+++ b/arch/mips/mips-boards/malta/Makefile
@@ -22,6 +22,7 @@
 obj-y := malta_int.o malta_platform.o malta_setup.o
 
 obj-$(CONFIG_MTD) += malta_mtd.o
+# FIXME FIXME FIXME
 obj-$(CONFIG_MIPS_MT_SMTC) += malta_smtc.o
 
 EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index dbe60eb55e29..e1744ae855ce 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -31,6 +31,7 @@
 #include <linux/kernel.h>
 #include <linux/random.h>
 
+#include <asm/traps.h>
 #include <asm/i8259.h>
 #include <asm/irq_cpu.h>
 #include <asm/irq_regs.h>
@@ -41,6 +42,14 @@
 #include <asm/mips-boards/generic.h>
 #include <asm/mips-boards/msc01_pci.h>
 #include <asm/msc01_ic.h>
+#include <asm/gic.h>
+#include <asm/gcmpregs.h>
+
+int gcmp_present = -1;
+int gic_present;
+static unsigned long _msc01_biu_base;
+static unsigned long _gcmp_base;
+static unsigned int ipi_map[NR_CPUS];
 
 static DEFINE_SPINLOCK(mips_irq_lock);
 
@@ -121,6 +130,17 @@ static void malta_hw0_irqdispatch(void)
         do_IRQ(MALTA_INT_BASE + irq);
 }
 
+static void malta_ipi_irqdispatch(void)
+{
+        int irq;
+
+        irq = gic_get_int();
+        if (irq < 0)
+                return;  /* interrupt has already been cleared */
+
+        do_IRQ(MIPS_GIC_IRQ_BASE + irq);
+}
+
 static void corehi_irqdispatch(void)
 {
         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
@@ -257,12 +277,61 @@ asmlinkage void plat_irq_dispatch(void)
 
         if (irq == MIPSCPU_INT_I8259A)
                 malta_hw0_irqdispatch();
+        else if (gic_present && ((1 << irq) & ipi_map[smp_processor_id()]))
+                malta_ipi_irqdispatch();
         else if (irq >= 0)
                 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
         else
                 spurious_interrupt();
 }
 
+#ifdef CONFIG_MIPS_MT_SMP
+
+
+#define GIC_MIPS_CPU_IPI_RESCHED_IRQ    3
+#define GIC_MIPS_CPU_IPI_CALL_IRQ       4
+
+#define MIPS_CPU_IPI_RESCHED_IRQ 0      /* SW int 0 for resched */
+#define C_RESCHED C_SW0
+#define MIPS_CPU_IPI_CALL_IRQ 1         /* SW int 1 for resched */
+#define C_CALL C_SW1
+static int cpu_ipi_resched_irq, cpu_ipi_call_irq;
+
+static void ipi_resched_dispatch(void)
+{
+        do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
+}
+
+static void ipi_call_dispatch(void)
+{
+        do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
+}
+
+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
+{
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
+{
+        smp_call_function_interrupt();
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction irq_resched = {
+        .handler        = ipi_resched_interrupt,
+        .flags          = IRQF_DISABLED|IRQF_PERCPU,
+        .name           = "IPI_resched"
+};
+
+static struct irqaction irq_call = {
+        .handler        = ipi_call_interrupt,
+        .flags          = IRQF_DISABLED|IRQF_PERCPU,
+        .name           = "IPI_call"
+};
+#endif /* CONFIG_MIPS_MT_SMP */
+
 static struct irqaction i8259irq = {
         .handler = no_action,
         .name = "XT-PIC cascade"
@@ -291,15 +360,90 @@ msc_irqmap_t __initdata msc_eicirqmap[] = {
         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 };
+
 int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
 
+/*
+ * This GIC specific tabular array defines the association between External
+ * Interrupts and CPUs/Core Interrupts. The nature of the External
+ * Interrupts is also defined here - polarity/trigger.
+ */
+static struct gic_intr_map gic_intr_map[] = {
+        { GIC_EXT_INTR(0),      X,      X,              X,              X,              0 },
+        { GIC_EXT_INTR(1),      X,      X,              X,              X,              0 },
+        { GIC_EXT_INTR(2),      X,      X,              X,              X,              0 },
+        { GIC_EXT_INTR(3),      0,      GIC_CPU_INT0,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(4),      0,      GIC_CPU_INT1,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(5),      0,      GIC_CPU_INT2,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(6),      0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(7),      0,      GIC_CPU_INT4,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(8),      0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(9),      0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(10),     X,      X,              X,              X,              0 },
+        { GIC_EXT_INTR(11),     X,      X,              X,              X,              0 },
+        { GIC_EXT_INTR(12),     0,      GIC_CPU_INT3,   GIC_POL_POS,    GIC_TRIG_LEVEL, 0 },
+        { GIC_EXT_INTR(13),     0,      GIC_MAP_TO_NMI_MSK,     GIC_POL_POS, GIC_TRIG_LEVEL,    0 },
+        { GIC_EXT_INTR(14),     0,      GIC_MAP_TO_NMI_MSK,     GIC_POL_POS, GIC_TRIG_LEVEL,    0 },
+        { GIC_EXT_INTR(15),     X,      X,              X,              X,              0 },
+        { GIC_EXT_INTR(16),     0,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+        { GIC_EXT_INTR(17),     0,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+        { GIC_EXT_INTR(18),     1,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+        { GIC_EXT_INTR(19),     1,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+        { GIC_EXT_INTR(20),     2,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+        { GIC_EXT_INTR(21),     2,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+        { GIC_EXT_INTR(22),     3,      GIC_CPU_INT1,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+        { GIC_EXT_INTR(23),     3,      GIC_CPU_INT2,   GIC_POL_POS, GIC_TRIG_EDGE,     1 },
+};
+
+/*
+ * GCMP needs to be detected before any SMP initialisation
+ */
+int __init gcmp_probe(unsigned long addr, unsigned long size)
+{
+        if (gcmp_present >= 0)
+                return gcmp_present;
+
+        _gcmp_base = (unsigned long) ioremap_nocache(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
+        _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
+        gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR;
+
+        if (gcmp_present)
+                printk(KERN_DEBUG "GCMP present\n");
+        return gcmp_present;
+}
+
+void __init fill_ipi_map(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
+                if (gic_intr_map[i].ipiflag && (gic_intr_map[i].cpunum != X))
+                        ipi_map[gic_intr_map[i].cpunum] |=
+                                (1 << (gic_intr_map[i].pin + 2));
+        }
+}
+
 void __init arch_init_irq(void)
 {
+        int gic_present, gcmp_present;
+
         init_i8259_irqs();
 
         if (!cpu_has_veic)
                 mips_cpu_irq_init();
 
+        gcmp_present = gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ);
+        if (gcmp_present)  {
+                GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
+                gic_present = 1;
+        } else {
+                _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ);
+                gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) &
+                MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF;
+        }
+        if (gic_present)
+                printk(KERN_DEBUG "GIC present\n");
+
         switch (mips_revision_sconid) {
         case MIPS_REVISION_SCON_SOCIT:
         case MIPS_REVISION_SCON_ROCIT:
@@ -360,4 +504,206 @@ void __init arch_init_irq(void)
                 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
                                                 &corehi_irqaction);
         }
+
+#if defined(CONFIG_MIPS_MT_SMP)
+        if (gic_present) {
+                /* FIXME */
+                int i;
+                struct {
+                        unsigned int resched;
+                        unsigned int call;
+                } ipiirq[] = {
+                        {
+                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE0,
+                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE0},
+                        {
+                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE1,
+                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE1
+                        }, {
+                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE2,
+                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE2
+                        }, {
+                                .resched = GIC_IPI_EXT_INTR_RESCHED_VPE3,
+                                .call =  GIC_IPI_EXT_INTR_CALLFNC_VPE3
+                        }
+                };
+#define NIPI (sizeof(ipiirq)/sizeof(ipiirq[0]))
+                fill_ipi_map();
+                gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
+                if (!gcmp_present) {
+                        /* Enable the GIC */
+                        i = REG(_msc01_biu_base, MSC01_SC_CFG);
+                        REG(_msc01_biu_base, MSC01_SC_CFG) =
+                                (i | (0x1 << MSC01_SC_CFG_GICENA_SHF));
+                        pr_debug("GIC Enabled\n");
+                }
+
+                /* set up ipi interrupts */
+                if (cpu_has_vint) {
+                        set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch);
+                        set_vi_handler(MIPSCPU_INT_IPI1, malta_ipi_irqdispatch);
+                }
+                /* Argh.. this really needs sorting out.. */
+                printk("CPU%d: status register was %08x\n", smp_processor_id(), read_c0_status());
+                write_c0_status(read_c0_status() | STATUSF_IP3 | STATUSF_IP4);
+                printk("CPU%d: status register now %08x\n", smp_processor_id(), read_c0_status());
+                write_c0_status(0x1100dc00);
+                printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status());
+                for (i = 0; i < NIPI; i++) {
+                        setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, &irq_resched);
+                        setup_irq(MIPS_GIC_IRQ_BASE + ipiirq[i].call, &irq_call);
+
+                        set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].resched, handle_percpu_irq);
+                        set_irq_handler(MIPS_GIC_IRQ_BASE + ipiirq[i].call, handle_percpu_irq);
+                }
+        } else {
+                /* set up ipi interrupts */
+                if (cpu_has_veic) {
+                        set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch);
+                        set_vi_handler (MSC01E_INT_SW1, ipi_call_dispatch);
+                        cpu_ipi_resched_irq = MSC01E_INT_SW0;
+                        cpu_ipi_call_irq = MSC01E_INT_SW1;
+                } else {
+                        if (cpu_has_vint) {
+                                set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch);
+                                set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch);
+                        }
+                        cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ;
+                        cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ;
+                }
+
+                setup_irq(cpu_ipi_resched_irq, &irq_resched);
+                setup_irq(cpu_ipi_call_irq, &irq_call);
+
+                set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq);
+                set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq);
+        }
+#endif
+}
+
+void malta_be_init(void)
+{
+        if (gcmp_present) {
+                /* Could change CM error mask register */
+        }
+}
+
+
+static char *tr[8] = {
+        "mem",  "gcr",  "gic",  "mmio",
+        "0x04", "0x05", "0x06", "0x07"
+};
+
+static char *mcmd[32] = {
+        [0x00] = "0x00",
+        [0x01] = "Legacy Write",
+        [0x02] = "Legacy Read",
+        [0x03] = "0x03",
+        [0x04] = "0x04",
+        [0x05] = "0x05",
+        [0x06] = "0x06",
+        [0x07] = "0x07",
+        [0x08] = "Coherent Read Own",
+        [0x09] = "Coherent Read Share",
+        [0x0a] = "Coherent Read Discard",
+        [0x0b] = "Coherent Ready Share Always",
+        [0x0c] = "Coherent Upgrade",
+        [0x0d] = "Coherent Writeback",
+        [0x0e] = "0x0e",
+        [0x0f] = "0x0f",
+        [0x10] = "Coherent Copyback",
+        [0x11] = "Coherent Copyback Invalidate",
+        [0x12] = "Coherent Invalidate",
+        [0x13] = "Coherent Write Invalidate",
+        [0x14] = "Coherent Completion Sync",
+        [0x15] = "0x15",
+        [0x16] = "0x16",
+        [0x17] = "0x17",
+        [0x18] = "0x18",
+        [0x19] = "0x19",
+        [0x1a] = "0x1a",
+        [0x1b] = "0x1b",
+        [0x1c] = "0x1c",
+        [0x1d] = "0x1d",
+        [0x1e] = "0x1e",
+        [0x1f] = "0x1f"
+};
+
+static char *core[8] = {
+        "Invalid/OK",   "Invalid/Data",
+        "Shared/OK",    "Shared/Data",
+        "Modified/OK",  "Modified/Data",
+        "Exclusive/OK", "Exclusive/Data"
+};
+
+static char *causes[32] = {
+        "None", "GC_WR_ERR", "GC_RD_ERR", "COH_WR_ERR",
+        "COH_RD_ERR", "MMIO_WR_ERR", "MMIO_RD_ERR", "0x07",
+        "0x08", "0x09", "0x0a", "0x0b",
+        "0x0c", "0x0d", "0x0e", "0x0f",
+        "0x10", "0x11", "0x12", "0x13",
+        "0x14", "0x15", "0x16", "INTVN_WR_ERR",
+        "INTVN_RD_ERR", "0x19", "0x1a", "0x1b",
+        "0x1c", "0x1d", "0x1e", "0x1f"
+};
+
+int malta_be_handler(struct pt_regs *regs, int is_fixup)
+{
+        /* This duplicates the handling in do_be which seems wrong */
+        int retval = is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL;
+
+        if (gcmp_present) {
+                unsigned long cm_error = GCMPGCB(GCMEC);
+                unsigned long cm_addr = GCMPGCB(GCMEA);
+                unsigned long cm_other = GCMPGCB(GCMEO);
+                unsigned long cause, ocause;
+                char buf[256];
+
+                cause = (cm_error & GCMP_GCB_GMEC_ERROR_TYPE_MSK);
+                if (cause != 0) {
+                        cause >>= GCMP_GCB_GMEC_ERROR_TYPE_SHF;
+                        if (cause < 16) {
+                                unsigned long cca_bits = (cm_error >> 15) & 7;
+                                unsigned long tr_bits = (cm_error >> 12) & 7;
+                                unsigned long mcmd_bits = (cm_error >> 7) & 0x1f;
+                                unsigned long stag_bits = (cm_error >> 3) & 15;
+                                unsigned long sport_bits = (cm_error >> 0) & 7;
+
+                                snprintf(buf, sizeof(buf),
+                                         "CCA=%lu TR=%s MCmd=%s STag=%lu "
+                                         "SPort=%lu\n",
+                                         cca_bits, tr[tr_bits], mcmd[mcmd_bits],
+                                         stag_bits, sport_bits);
+                        } else {
+                                /* glob state & sresp together */
+                                unsigned long c3_bits = (cm_error >> 18) & 7;
+                                unsigned long c2_bits = (cm_error >> 15) & 7;
+                                unsigned long c1_bits = (cm_error >> 12) & 7;
+                                unsigned long c0_bits = (cm_error >> 9) & 7;
+                                unsigned long sc_bit = (cm_error >> 8) & 1;
+                                unsigned long mcmd_bits = (cm_error >> 3) & 0x1f;
+                                unsigned long sport_bits = (cm_error >> 0) & 7;
+                                snprintf(buf, sizeof(buf),
+                                         "C3=%s C2=%s C1=%s C0=%s SC=%s "
+                                         "MCmd=%s SPort=%lu\n",
+                                         core[c3_bits], core[c2_bits],
+                                         core[c1_bits], core[c0_bits],
+                                         sc_bit ? "True" : "False",
+                                         mcmd[mcmd_bits], sport_bits);
+                        }
+
+                        ocause = (cm_other & GCMP_GCB_GMEO_ERROR_2ND_MSK) >>
+                                 GCMP_GCB_GMEO_ERROR_2ND_SHF;
+
+                        printk("CM_ERROR=%08lx %s <%s>\n", cm_error,
+                               causes[cause], buf);
+                        printk("CM_ADDR =%08lx\n", cm_addr);
+                        printk("CM_OTHER=%08lx %s\n", cm_other, causes[ocause]);
+
+                        /* reprime cause register */
+                        GCMPGCB(GCMEC) = 0;
+                }
+        }
+
+        return retval;
 }
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 2cd8f5734b36..4a0f21c76e7b 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -36,6 +36,9 @@
 #include <linux/console.h>
 #endif
 
+extern void malta_be_init(void);
+extern int malta_be_handler(struct pt_regs *regs, int is_fixup);
+
 struct resource standard_io_resources[] = {
         {
                 .name = "dma1",
@@ -220,4 +223,7 @@ void __init plat_mem_setup(void)
         screen_info_setup();
 #endif
         mips_reboot_setup();
+
+        board_be_init = malta_be_init;
+        board_be_handler = malta_be_handler;
 }