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authorRalf Baechle <ralf@linux-mips.org>2006-05-18 07:38:47 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-19 12:39:19 -0400
commitb0b0e13e7dd309be13ab9324e67893e62b136e44 (patch)
tree522f2ee785c8ab5600a254cabe8b2d0326425a0c /arch/mips/mips-boards
parentc583122c26ad04bb2379933dc5acc8b9479d6c67 (diff)
[MIPS] Remove unused instances of prom_build_cpu_map.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards')
-rw-r--r--arch/mips/mips-boards/malta/malta_smp.c19
-rw-r--r--arch/mips/mips-boards/sim/sim_smp.c21
2 files changed, 0 insertions, 40 deletions
diff --git a/arch/mips/mips-boards/malta/malta_smp.c b/arch/mips/mips-boards/malta/malta_smp.c
index 6c6c8eeedbce..cf967170fe29 100644
--- a/arch/mips/mips-boards/malta/malta_smp.c
+++ b/arch/mips/mips-boards/malta/malta_smp.c
@@ -34,25 +34,6 @@ void core_send_ipi(int cpu, unsigned int action)
34} 34}
35 35
36/* 36/*
37 * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
38 */
39
40void __init prom_build_cpu_map(void)
41{
42 int nextslot;
43
44 /*
45 * As of November, 2004, MIPSsim only simulates one core
46 * at a time. However, that core may be a MIPS MT core
47 * with multiple virtual processors and thread contexts.
48 */
49
50 if (read_c0_config3() & (1<<2)) {
51 nextslot = mipsmt_build_cpu_map(1);
52 }
53}
54
55/*
56 * Platform "CPU" startup hook 37 * Platform "CPU" startup hook
57 */ 38 */
58 39
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c
index b7084e7c4bf9..004070956cca 100644
--- a/arch/mips/mips-boards/sim/sim_smp.c
+++ b/arch/mips/mips-boards/sim/sim_smp.c
@@ -51,27 +51,6 @@ void core_send_ipi(int cpu, unsigned int action)
51} 51}
52 52
53/* 53/*
54 * Detect available CPUs/VPEs/TCs and populate phys_cpu_present_map
55 */
56
57void __init prom_build_cpu_map(void)
58{
59#ifdef CONFIG_MIPS_MT_SMTC
60 int nextslot;
61
62 /*
63 * As of November, 2004, MIPSsim only simulates one core
64 * at a time. However, that core may be a MIPS MT core
65 * with multiple virtual processors and thread contexts.
66 */
67
68 if (read_c0_config3() & (1<<2)) {
69 nextslot = mipsmt_build_cpu_map(1);
70 }
71#endif /* CONFIG_MIPS_MT_SMTC */
72}
73
74/*
75 * Platform "CPU" startup hook 54 * Platform "CPU" startup hook
76 */ 55 */
77 56