[MIPS] War on whitespace: cleanup initial spaces followed by tabs.

    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

4 files changed, 4 insertions, 4 deletions

diff --git a/arch/mips/mips-boards/generic/mipsIRQ.S b/arch/mips/mips-boards/generic/mipsIRQ.S
index a397ecb872d6..ddd5c73a2971 100644
--- a/arch/mips/mips-boards/generic/mipsIRQ.S
+++ b/arch/mips/mips-boards/generic/mipsIRQ.S
@@ -98,7 +98,7 @@
         and     s0, s1
 
 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-        .set    mips32
+        .set    mips32
         clz     a0, s0
         .set    mips0
         negu    a0
diff --git a/arch/mips/mips-boards/sim/sim_IRQ.c b/arch/mips/mips-boards/sim/sim_IRQ.c
index 9987a85aabeb..5b84c7fe1022 100644
--- a/arch/mips/mips-boards/sim/sim_IRQ.c
+++ b/arch/mips/mips-boards/sim/sim_IRQ.c
@@ -96,7 +96,7 @@
          andi   a0, s0, CAUSEF_IP3      # delay slot, check hw1 interrupt
 #else
         beq     a0, zero, 1f            # delay slot, check hw3 interrupt
-         andi   a0, s0, CAUSEF_IP5
+         andi   a0, s0, CAUSEF_IP5
 #endif
 
         /* Wheee, combined hardware level zero interrupt. */
diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S
index 835f0387fcd4..da52297a2216 100644
--- a/arch/mips/mips-boards/sim/sim_irq.S
+++ b/arch/mips/mips-boards/sim/sim_irq.S
@@ -42,7 +42,7 @@
         and     s0, s1
 
 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-        .set    mips32
+        .set    mips32
         clz     a0, s0
         .set    mips0
         negu    a0
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c
index 19824359f5de..a9f0c2bfe4ad 100644
--- a/arch/mips/mips-boards/sim/sim_smp.c
+++ b/arch/mips/mips-boards/sim/sim_smp.c
@@ -115,7 +115,7 @@ void prom_prepare_cpus(unsigned int max_cpus)
 #ifdef CONFIG_MIPS_MT_SMTC
         void mipsmt_prepare_cpus(int c);
         /*
-         * As noted above, we can assume a single CPU for now
+         * As noted above, we can assume a single CPU for now
          * but it may be multithreaded.
          */