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authorRalf Baechle <ralf@linux-mips.org>2006-03-11 03:18:41 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-03-21 08:27:47 -0500
commita3dddd560ee936495466d85ecc97490d171e8d31 (patch)
treee9b5d778b5249ce348d2285a9b886b83c510d813 /arch/mips/mips-boards/sim
parent59b3e8e9aac69d2d02853acac7e2affdfbabca50 (diff)
[MIPS] War on whitespace: cleanup initial spaces followed by tabs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/sim')
-rw-r--r--arch/mips/mips-boards/sim/sim_IRQ.c2
-rw-r--r--arch/mips/mips-boards/sim/sim_irq.S2
-rw-r--r--arch/mips/mips-boards/sim/sim_smp.c2
3 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/mips-boards/sim/sim_IRQ.c b/arch/mips/mips-boards/sim/sim_IRQ.c
index 9987a85aabeb..5b84c7fe1022 100644
--- a/arch/mips/mips-boards/sim/sim_IRQ.c
+++ b/arch/mips/mips-boards/sim/sim_IRQ.c
@@ -96,7 +96,7 @@
96 andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt 96 andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
97#else 97#else
98 beq a0, zero, 1f # delay slot, check hw3 interrupt 98 beq a0, zero, 1f # delay slot, check hw3 interrupt
99 andi a0, s0, CAUSEF_IP5 99 andi a0, s0, CAUSEF_IP5
100#endif 100#endif
101 101
102 /* Wheee, combined hardware level zero interrupt. */ 102 /* Wheee, combined hardware level zero interrupt. */
diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S
index 835f0387fcd4..da52297a2216 100644
--- a/arch/mips/mips-boards/sim/sim_irq.S
+++ b/arch/mips/mips-boards/sim/sim_irq.S
@@ -42,7 +42,7 @@
42 and s0, s1 42 and s0, s1
43 43
44#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 44#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
45 .set mips32 45 .set mips32
46 clz a0, s0 46 clz a0, s0
47 .set mips0 47 .set mips0
48 negu a0 48 negu a0
diff --git a/arch/mips/mips-boards/sim/sim_smp.c b/arch/mips/mips-boards/sim/sim_smp.c
index 19824359f5de..a9f0c2bfe4ad 100644
--- a/arch/mips/mips-boards/sim/sim_smp.c
+++ b/arch/mips/mips-boards/sim/sim_smp.c
@@ -115,7 +115,7 @@ void prom_prepare_cpus(unsigned int max_cpus)
115#ifdef CONFIG_MIPS_MT_SMTC 115#ifdef CONFIG_MIPS_MT_SMTC
116 void mipsmt_prepare_cpus(int c); 116 void mipsmt_prepare_cpus(int c);
117 /* 117 /*
118 * As noted above, we can assume a single CPU for now 118 * As noted above, we can assume a single CPU for now
119 * but it may be multithreaded. 119 * but it may be multithreaded.
120 */ 120 */
121 121