aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mips-boards/sead
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2006-04-03 12:56:36 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-04-18 22:14:21 -0400
commite4ac58afdfac792c0583af30dbd9eae53e24c78b (patch)
tree7517bef2c515fc630e4d3d238867b91cde96f558 /arch/mips/mips-boards/sead
parentd35d473c25d43d7db3e5e18b66d558d2a631cca8 (diff)
[MIPS] Rewrite all the assembler interrupt handlers to C.
Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/sead')
-rw-r--r--arch/mips/mips-boards/sead/Makefile2
-rw-r--r--arch/mips/mips-boards/sead/sead-irq.S111
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c86
3 files changed, 83 insertions, 116 deletions
diff --git a/arch/mips/mips-boards/sead/Makefile b/arch/mips/mips-boards/sead/Makefile
index 01780b605346..224bb848f16b 100644
--- a/arch/mips/mips-boards/sead/Makefile
+++ b/arch/mips/mips-boards/sead/Makefile
@@ -23,4 +23,4 @@
23# under Linux. 23# under Linux.
24# 24#
25 25
26obj-y := sead_int.o sead-irq.o sead_setup.o 26obj-y := sead_int.o sead_setup.o
diff --git a/arch/mips/mips-boards/sead/sead-irq.S b/arch/mips/mips-boards/sead/sead-irq.S
deleted file mode 100644
index d5dea1d2e220..000000000000
--- a/arch/mips/mips-boards/sead/sead-irq.S
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 * Interrupt exception dispatch code.
23 *
24 */
25#include <linux/config.h>
26
27#include <asm/asm.h>
28#include <asm/mipsregs.h>
29#include <asm/regdef.h>
30#include <asm/stackframe.h>
31#include <asm/mips-boards/seadint.h>
32
33/*
34 * IRQs on the SEAD board look basically are combined together on hardware
35 * interrupt 0 (MIPS IRQ 2)) like:
36 *
37 * MIPS IRQ Source
38 * -------- ------
39 * 0 Software (ignored)
40 * 1 Software (ignored)
41 * 2 UART0 (hw0)
42 * 3 UART1 (hw1)
43 * 4 Hardware (ignored)
44 * 5 Hardware (ignored)
45 * 6 Hardware (ignored)
46 * 7 R4k timer (what we use)
47 *
48 * We handle the IRQ according to _our_ priority which is:
49 *
50 * Highest ---- R4k Timer
51 * Lowest ---- Combined hardware interrupt
52 *
53 * then we just return, if multiple IRQs are pending then we will just take
54 * another exception, big deal.
55 */
56
57 .text
58 .set noreorder
59 .set noat
60 .align 5
61 NESTED(mipsIRQ, PT_SIZE, sp)
62 SAVE_ALL
63 CLI
64 .set at
65
66 mfc0 s0, CP0_CAUSE # get irq bits
67 mfc0 s1, CP0_STATUS # get irq mask
68 andi s0, ST0_IM # CAUSE.CE may be non-zero!
69 and s0, s1
70
71#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
72 .set mips32
73 clz a0, s0
74 .set mips0
75 negu a0
76 addu a0, 31-CAUSEB_IP
77 bltz a0, spurious
78#else
79 beqz s0, spurious
80 li a0, 7
81
82 and t0, s0, 0xf000
83 sltiu t0, t0, 1
84 sll t0, 2
85 subu a0, t0
86 sll s0, t0
87
88 and t0, s0, 0xc000
89 sltiu t0, t0, 1
90 sll t0, 1
91 subu a0, t0
92 sll s0, t0
93
94 and t0, s0, 0x8000
95 sltiu t0, t0, 1
96 # sll t0, 0
97 subu a0, t0
98 # sll s0, t0
99#endif
100
101 addu a0, MIPSCPU_INT_BASE
102 jal do_IRQ
103 move a1, sp
104
105 j ret_from_irq
106 nop
107
108spurious:
109 j spurious_interrupt
110 nop
111 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 90fda0d9915f..9168d934c661 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -24,16 +24,94 @@
24#include <linux/irq.h> 24#include <linux/irq.h>
25 25
26#include <asm/irq_cpu.h> 26#include <asm/irq_cpu.h>
27#include <asm/mipsregs.h>
27#include <asm/system.h> 28#include <asm/system.h>
28 29
29#include <asm/mips-boards/seadint.h> 30#include <asm/mips-boards/seadint.h>
30 31
31extern asmlinkage void mipsIRQ(void); 32static inline int clz(unsigned long x)
33{
34 __asm__ (
35 " .set push \n"
36 " .set mips32 \n"
37 " clz %0, %1 \n"
38 " .set pop \n"
39 : "=r" (x)
40 : "r" (x));
41
42 return x;
43}
44
45/*
46 * Version of ffs that only looks at bits 12..15.
47 */
48static inline unsigned int irq_ffs(unsigned int pending)
49{
50#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
51 return -clz(pending) + 31 - CAUSEB_IP;
52#else
53 unsigned int a0 = 7;
54 unsigned int t0;
55
56 t0 = s0 & 0xf000;
57 t0 = t0 < 1;
58 t0 = t0 << 2;
59 a0 = a0 - t0;
60 s0 = s0 << t0;
61
62 t0 = s0 & 0xc000;
63 t0 = t0 < 1;
64 t0 = t0 << 1;
65 a0 = a0 - t0;
66 s0 = s0 << t0;
67
68 t0 = s0 & 0x8000;
69 t0 = t0 < 1;
70 //t0 = t0 << 2;
71 a0 = a0 - t0;
72 //s0 = s0 << t0;
73
74 return a0;
75#endif
76}
77
78/*
79 * IRQs on the SEAD board look basically are combined together on hardware
80 * interrupt 0 (MIPS IRQ 2)) like:
81 *
82 * MIPS IRQ Source
83 * -------- ------
84 * 0 Software (ignored)
85 * 1 Software (ignored)
86 * 2 UART0 (hw0)
87 * 3 UART1 (hw1)
88 * 4 Hardware (ignored)
89 * 5 Hardware (ignored)
90 * 6 Hardware (ignored)
91 * 7 R4k timer (what we use)
92 *
93 * We handle the IRQ according to _our_ priority which is:
94 *
95 * Highest ---- R4k Timer
96 * Lowest ---- Combined hardware interrupt
97 *
98 * then we just return, if multiple IRQs are pending then we will just take
99 * another exception, big deal.
100 */
101asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
102{
103 unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
104 int irq;
105
106 irq = irq_ffs(pending);
107
108 if (irq >= 0)
109 do_IRQ(MIPSCPU_INT_BASE + irq, regs);
110 else
111 spurious_interrupt(regs);
112}
32 113
33void __init arch_init_irq(void) 114void __init arch_init_irq(void)
34{ 115{
35 mips_cpu_irq_init(MIPSCPU_INT_BASE); 116 mips_cpu_irq_init(MIPSCPU_INT_BASE);
36
37 /* Now safe to set the exception vector. */
38 set_except_vector(0, mipsIRQ);
39} 117}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 02:54:56 -0500