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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:15 -0400
commit49a89efbbbcc178a39555c43bd59a7593c429664 (patch)
tree93ab78ec340d3f2fe23f9f853edd0bd62dcc64bb /arch/mips/mips-boards/malta
parent10cc3529072d5415fb040018a8a99aa7a60190b6 (diff)
[MIPS] Fix "no space between function name and open parenthesis" warnings.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/malta')
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c34
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c10
2 files changed, 22 insertions, 22 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index b73f21823c5e..8232392750a8 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -178,7 +178,7 @@ static void corehi_irqdispatch(void)
178 178
179static inline int clz(unsigned long x) 179static inline int clz(unsigned long x)
180{ 180{
181 __asm__ ( 181 __asm__(
182 " .set push \n" 182 " .set push \n"
183 " .set mips32 \n" 183 " .set mips32 \n"
184 " clz %0, %1 \n" 184 " clz %0, %1 \n"
@@ -303,32 +303,32 @@ void __init arch_init_irq(void)
303 case MIPS_REVISION_SCON_SOCIT: 303 case MIPS_REVISION_SCON_SOCIT:
304 case MIPS_REVISION_SCON_ROCIT: 304 case MIPS_REVISION_SCON_ROCIT:
305 if (cpu_has_veic) 305 if (cpu_has_veic)
306 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 306 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
307 else 307 else
308 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 308 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
309 break; 309 break;
310 310
311 case MIPS_REVISION_SCON_SOCITSC: 311 case MIPS_REVISION_SCON_SOCITSC:
312 case MIPS_REVISION_SCON_SOCITSCP: 312 case MIPS_REVISION_SCON_SOCITSCP:
313 if (cpu_has_veic) 313 if (cpu_has_veic)
314 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 314 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
315 else 315 else
316 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 316 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
317 } 317 }
318 318
319 if (cpu_has_veic) { 319 if (cpu_has_veic) {
320 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); 320 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
321 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); 321 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
322 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 322 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
323 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 323 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
324 } 324 }
325 else if (cpu_has_vint) { 325 else if (cpu_has_vint) {
326 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 326 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
327 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); 327 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
328#ifdef CONFIG_MIPS_MT_SMTC 328#ifdef CONFIG_MIPS_MT_SMTC
329 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, 329 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
330 (0x100 << MIPSCPU_INT_I8259A)); 330 (0x100 << MIPSCPU_INT_I8259A));
331 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 331 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
333 /* 333 /*
334 * Temporary hack to ensure that the subsidiary device 334 * Temporary hack to ensure that the subsidiary device
@@ -343,12 +343,12 @@ void __init arch_init_irq(void)
343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); 343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
344 } 344 }
345#else /* Not SMTC */ 345#else /* Not SMTC */
346 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 346 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
347 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 347 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
348#endif /* CONFIG_MIPS_MT_SMTC */ 348#endif /* CONFIG_MIPS_MT_SMTC */
349 } 349 }
350 else { 350 else {
351 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 351 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
352 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 352 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
353 } 353 }
354} 354}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index a5a5a43a1984..e243d5efcb38 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -99,7 +99,7 @@ void __init plat_mem_setup(void)
99 enable_dma(4); 99 enable_dma(4);
100 100
101#ifdef CONFIG_KGDB 101#ifdef CONFIG_KGDB
102 kgdb_config (); 102 kgdb_config();
103#endif 103#endif
104 104
105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
@@ -108,7 +108,7 @@ void __init plat_mem_setup(void)
108 argptr = prom_getcmdline(); 108 argptr = prom_getcmdline();
109 if (strstr(argptr, "debug")) { 109 if (strstr(argptr, "debug")) {
110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
111 printk ("Enabled Bonito debug mode\n"); 111 printk("Enabled Bonito debug mode\n");
112 } 112 }
113 else 113 else
114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
@@ -159,14 +159,14 @@ void __init plat_mem_setup(void)
159 if (pciclock != 33 && !strstr (argptr, "idebus=")) { 159 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); 160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
161 argptr += strlen(argptr); 161 argptr += strlen(argptr);
162 sprintf (argptr, " idebus=%d", pciclock); 162 sprintf(argptr, " idebus=%d", pciclock);
163 if (pciclock < 20 || pciclock > 66) 163 if (pciclock < 20 || pciclock > 66)
164 printk ("WARNING: IDE timing calculations will be incorrect\n"); 164 printk("WARNING: IDE timing calculations will be incorrect\n");
165 } 165 }
166 } 166 }
167#endif 167#endif
168#ifdef CONFIG_BLK_DEV_FD 168#ifdef CONFIG_BLK_DEV_FD
169 fd_activate (); 169 fd_activate();
170#endif 170#endif
171#ifdef CONFIG_VT 171#ifdef CONFIG_VT
172#if defined(CONFIG_VGA_CONSOLE) 172#if defined(CONFIG_VGA_CONSOLE)