aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/mips-boards/malta
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2007-06-20 17:27:10 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-06-20 17:27:10 -0400
commit3b1d4ed5353af04d6aa20be2701727b9cdb2ac61 (patch)
treee4a3335c925abd933f1650e1ee4786e6bfad8f35 /arch/mips/mips-boards/malta
parent7c8545e98468c53809fc06788a3b9a34dff05240 (diff)
[MIPS] Don't drag a platform specific header into generic arch code.
For some platforms it's definitions may conflict. So that's the one-liner. The rest is 10 square kilometers of collateral damage fixup this include used to paper over. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/malta')
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 1668cc21d5b5..c78d48349600 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -257,7 +257,7 @@ asmlinkage void plat_irq_dispatch(void)
257 if (irq == MIPSCPU_INT_I8259A) 257 if (irq == MIPSCPU_INT_I8259A)
258 malta_hw0_irqdispatch(); 258 malta_hw0_irqdispatch();
259 else if (irq > 0) 259 else if (irq > 0)
260 do_IRQ(MIPSCPU_INT_BASE + irq); 260 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
261 else 261 else
262 spurious_interrupt(); 262 spurious_interrupt();
263} 263}
@@ -326,17 +326,17 @@ void __init arch_init_irq(void)
326 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 326 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
327 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); 327 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
328#ifdef CONFIG_MIPS_MT_SMTC 328#ifdef CONFIG_MIPS_MT_SMTC
329 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq, 329 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
330 (0x100 << MIPSCPU_INT_I8259A)); 330 (0x100 << MIPSCPU_INT_I8259A));
331 setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, 331 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
333#else /* Not SMTC */ 333#else /* Not SMTC */
334 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); 334 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
335 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 335 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
336#endif /* CONFIG_MIPS_MT_SMTC */ 336#endif /* CONFIG_MIPS_MT_SMTC */
337 } 337 }
338 else { 338 else {
339 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq); 339 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
340 setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 340 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
341 } 341 }
342} 342}