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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/mips-boards/malta
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/mips-boards/malta')
-rw-r--r--arch/mips/mips-boards/malta/Makefile22
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c187
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c231
3 files changed, 440 insertions, 0 deletions
diff --git a/arch/mips/mips-boards/malta/Makefile b/arch/mips/mips-boards/malta/Makefile
new file mode 100644
index 000000000000..fd4c143c0e2f
--- /dev/null
+++ b/arch/mips/mips-boards/malta/Makefile
@@ -0,0 +1,22 @@
1#
2# Carsten Langgaard, carstenl@mips.com
3# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4#
5# This program is free software; you can distribute it and/or modify it
6# under the terms of the GNU General Public License (Version 2) as
7# published by the Free Software Foundation.
8#
9# This program is distributed in the hope it will be useful, but WITHOUT
10# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12# for more details.
13#
14# You should have received a copy of the GNU General Public License along
15# with this program; if not, write to the Free Software Foundation, Inc.,
16# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17#
18# Makefile for the MIPS Malta specific kernel interface routines
19# under Linux.
20#
21
22obj-y := malta_int.o malta_setup.o
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
new file mode 100644
index 000000000000..dd2db35966bc
--- /dev/null
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -0,0 +1,187 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
4 * Copyright (C) 2001 Ralf Baechle
5 *
6 * This program is free software; you can distribute it and/or modify it
7 * under the terms of the GNU General Public License (Version 2) as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, write to the Free Software Foundation, Inc.,
17 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
18 *
19 * Routines for generic manipulation of the interrupts found on the MIPS
20 * Malta board.
21 * The interrupt controller is located in the South Bridge a PIIX4 device
22 * with two internal 82C95 interrupt controllers.
23 */
24#include <linux/init.h>
25#include <linux/irq.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28#include <linux/interrupt.h>
29#include <linux/kernel_stat.h>
30#include <linux/random.h>
31
32#include <asm/i8259.h>
33#include <asm/io.h>
34#include <asm/mips-boards/malta.h>
35#include <asm/mips-boards/maltaint.h>
36#include <asm/mips-boards/piix4.h>
37#include <asm/gt64120.h>
38#include <asm/mips-boards/generic.h>
39#include <asm/mips-boards/msc01_pci.h>
40
41extern asmlinkage void mipsIRQ(void);
42
43static DEFINE_SPINLOCK(mips_irq_lock);
44
45static inline int mips_pcibios_iack(void)
46{
47 int irq;
48 u32 dummy;
49
50 /*
51 * Determine highest priority pending interrupt by performing
52 * a PCI Interrupt Acknowledge cycle.
53 */
54 switch(mips_revision_corid) {
55 case MIPS_REVISION_CORID_CORE_MSC:
56 case MIPS_REVISION_CORID_CORE_FPGA2:
57 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
58 MSC_READ(MSC01_PCI_IACK, irq);
59 irq &= 0xff;
60 break;
61 case MIPS_REVISION_CORID_QED_RM5261:
62 case MIPS_REVISION_CORID_CORE_LV:
63 case MIPS_REVISION_CORID_CORE_FPGA:
64 case MIPS_REVISION_CORID_CORE_FPGAR2:
65 irq = GT_READ(GT_PCI0_IACK_OFS);
66 irq &= 0xff;
67 break;
68 case MIPS_REVISION_CORID_BONITO64:
69 case MIPS_REVISION_CORID_CORE_20K:
70 case MIPS_REVISION_CORID_CORE_EMUL_BON:
71 /* The following will generate a PCI IACK cycle on the
72 * Bonito controller. It's a little bit kludgy, but it
73 * was the easiest way to implement it in hardware at
74 * the given time.
75 */
76 BONITO_PCIMAP_CFG = 0x20000;
77
78 /* Flush Bonito register block */
79 dummy = BONITO_PCIMAP_CFG;
80 iob(); /* sync */
81
82 irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
83 iob(); /* sync */
84 irq &= 0xff;
85 BONITO_PCIMAP_CFG = 0;
86 break;
87 default:
88 printk("Unknown Core card, don't know the system controller.\n");
89 return -1;
90 }
91 return irq;
92}
93
94static inline int get_int(int *irq)
95{
96 unsigned long flags;
97
98 spin_lock_irqsave(&mips_irq_lock, flags);
99
100 *irq = mips_pcibios_iack();
101
102 /*
103 * IRQ7 is used to detect spurious interrupts.
104 * The interrupt acknowledge cycle returns IRQ7, if no
105 * interrupts is requested.
106 * We can differentiate between this situation and a
107 * "Normal" IRQ7 by reading the ISR.
108 */
109 if (*irq == 7)
110 {
111 outb(PIIX4_OCW3_SEL | PIIX4_OCW3_ISR,
112 PIIX4_ICTLR1_OCW3);
113 if (!(inb(PIIX4_ICTLR1_OCW3) & (1 << 7))) {
114 spin_unlock_irqrestore(&mips_irq_lock, flags);
115 printk("We got a spurious interrupt from PIIX4.\n");
116 atomic_inc(&irq_err_count);
117 return -1; /* Spurious interrupt. */
118 }
119 }
120
121 spin_unlock_irqrestore(&mips_irq_lock, flags);
122
123 return 0;
124}
125
126void malta_hw0_irqdispatch(struct pt_regs *regs)
127{
128 int irq;
129
130 if (get_int(&irq))
131 return; /* interrupt has already been cleared */
132
133 do_IRQ(irq, regs);
134}
135
136void corehi_irqdispatch(struct pt_regs *regs)
137{
138 unsigned int data,datahi;
139
140 /* Mask out corehi interrupt. */
141 clear_c0_status(IE_IRQ3);
142
143 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
144 printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
145, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
146 switch(mips_revision_corid) {
147 case MIPS_REVISION_CORID_CORE_MSC:
148 case MIPS_REVISION_CORID_CORE_FPGA2:
149 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
150 break;
151 case MIPS_REVISION_CORID_QED_RM5261:
152 case MIPS_REVISION_CORID_CORE_LV:
153 case MIPS_REVISION_CORID_CORE_FPGA:
154 case MIPS_REVISION_CORID_CORE_FPGAR2:
155 data = GT_READ(GT_INTRCAUSE_OFS);
156 printk("GT_INTRCAUSE = %08x\n", data);
157 data = GT_READ(GT_CPUERR_ADDRLO_OFS);
158 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
159 printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, data);
160 break;
161 case MIPS_REVISION_CORID_BONITO64:
162 case MIPS_REVISION_CORID_CORE_20K:
163 case MIPS_REVISION_CORID_CORE_EMUL_BON:
164 data = BONITO_INTISR;
165 printk("BONITO_INTISR = %08x\n", data);
166 data = BONITO_INTEN;
167 printk("BONITO_INTEN = %08x\n", data);
168 data = BONITO_INTPOL;
169 printk("BONITO_INTPOL = %08x\n", data);
170 data = BONITO_INTEDGE;
171 printk("BONITO_INTEDGE = %08x\n", data);
172 data = BONITO_INTSTEER;
173 printk("BONITO_INTSTEER = %08x\n", data);
174 data = BONITO_PCICMD;
175 printk("BONITO_PCICMD = %08x\n", data);
176 break;
177 }
178
179 /* We die here*/
180 die("CoreHi interrupt", regs);
181}
182
183void __init arch_init_irq(void)
184{
185 set_except_vector(0, mipsIRQ);
186 init_i8259_irqs();
187}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
new file mode 100644
index 000000000000..3377e66de9eb
--- /dev/null
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -0,0 +1,231 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 */
18#include <linux/config.h>
19#include <linux/init.h>
20#include <linux/sched.h>
21#include <linux/ioport.h>
22#include <linux/pci.h>
23#include <linux/tty.h>
24
25#ifdef CONFIG_MTD
26#include <linux/mtd/partitions.h>
27#include <linux/mtd/physmap.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/map.h>
30#endif
31
32#include <asm/cpu.h>
33#include <asm/bootinfo.h>
34#include <asm/irq.h>
35#include <asm/mips-boards/generic.h>
36#include <asm/mips-boards/prom.h>
37#include <asm/mips-boards/malta.h>
38#include <asm/mips-boards/maltaint.h>
39#include <asm/dma.h>
40#include <asm/time.h>
41#include <asm/traps.h>
42#ifdef CONFIG_VT
43#include <linux/console.h>
44#endif
45
46extern void mips_reboot_setup(void);
47extern void mips_time_init(void);
48extern void mips_timer_setup(struct irqaction *irq);
49extern unsigned long mips_rtc_get_time(void);
50
51#ifdef CONFIG_KGDB
52extern void kgdb_config(void);
53#endif
54
55struct resource standard_io_resources[] = {
56 { "dma1", 0x00, 0x1f, IORESOURCE_BUSY },
57 { "timer", 0x40, 0x5f, IORESOURCE_BUSY },
58 { "keyboard", 0x60, 0x6f, IORESOURCE_BUSY },
59 { "dma page reg", 0x80, 0x8f, IORESOURCE_BUSY },
60 { "dma2", 0xc0, 0xdf, IORESOURCE_BUSY },
61};
62
63#ifdef CONFIG_MTD
64static struct mtd_partition malta_mtd_partitions[] = {
65 {
66 .name = "YAMON",
67 .offset = 0x0,
68 .size = 0x100000,
69 .mask_flags = MTD_WRITEABLE
70 },
71 {
72 .name = "User FS",
73 .offset = 0x100000,
74 .size = 0x2e0000
75 },
76 {
77 .name = "Board Config",
78 .offset = 0x3e0000,
79 .size = 0x020000,
80 .mask_flags = MTD_WRITEABLE
81 }
82};
83
84#define number_partitions (sizeof(malta_mtd_partitions)/sizeof(struct mtd_partition))
85#endif
86
87const char *get_system_type(void)
88{
89 return "MIPS Malta";
90}
91
92#ifdef CONFIG_BLK_DEV_FD
93void __init fd_activate(void)
94{
95 /*
96 * Activate Floppy Controller in the SMSC FDC37M817 Super I/O
97 * Controller.
98 * Done by YAMON 2.00 onwards
99 */
100 /* Entering config state. */
101 SMSC_WRITE(SMSC_CONFIG_ENTER, SMSC_CONFIG_REG);
102
103 /* Activate floppy controller. */
104 SMSC_WRITE(SMSC_CONFIG_DEVNUM, SMSC_CONFIG_REG);
105 SMSC_WRITE(SMSC_CONFIG_DEVNUM_FLOPPY, SMSC_DATA_REG);
106 SMSC_WRITE(SMSC_CONFIG_ACTIVATE, SMSC_CONFIG_REG);
107 SMSC_WRITE(SMSC_CONFIG_ACTIVATE_ENABLE, SMSC_DATA_REG);
108
109 /* Exit config state. */
110 SMSC_WRITE(SMSC_CONFIG_EXIT, SMSC_CONFIG_REG);
111}
112#endif
113
114static int __init malta_setup(void)
115{
116 unsigned int i;
117
118 /* Request I/O space for devices used on the Malta board. */
119 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
120 request_resource(&ioport_resource, standard_io_resources+i);
121
122 /*
123 * Enable DMA channel 4 (cascade channel) in the PIIX4 south bridge.
124 */
125 enable_dma(4);
126
127#ifdef CONFIG_KGDB
128 kgdb_config ();
129#endif
130
131 if ((mips_revision_corid == MIPS_REVISION_CORID_BONITO64) ||
132 (mips_revision_corid == MIPS_REVISION_CORID_CORE_20K) ||
133 (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL_BON)) {
134 char *argptr;
135
136 argptr = prom_getcmdline();
137 if (strstr(argptr, "debug")) {
138 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
139 printk ("Enabled Bonito debug mode\n");
140 }
141 else
142 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
143
144#ifdef CONFIG_DMA_COHERENT
145 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
146 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
147 printk("Enabled Bonito CPU coherency\n");
148
149 argptr = prom_getcmdline();
150 if (strstr(argptr, "iobcuncached")) {
151 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
152 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
153 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
154 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
155 printk("Disabled Bonito IOBC coherency\n");
156 }
157 else {
158 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
159 BONITO_PCIMEMBASECFG |=
160 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
161 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
162 printk("Disabled Bonito IOBC coherency\n");
163 }
164 }
165 else
166 panic("Hardware DMA cache coherency not supported");
167
168#endif
169 }
170#ifdef CONFIG_DMA_COHERENT
171 else {
172 panic("Hardware DMA cache coherency not supported");
173 }
174#endif
175
176#ifdef CONFIG_BLK_DEV_IDE
177 /* Check PCI clock */
178 {
179 int jmpr = (*((volatile unsigned int *)ioremap(MALTA_JMPRS_REG, sizeof(unsigned int))) >> 2) & 0x07;
180 static const int pciclocks[] __initdata = {
181 33, 20, 25, 30, 12, 16, 37, 10
182 };
183 int pciclock = pciclocks[jmpr];
184 char *argptr = prom_getcmdline();
185
186 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
187 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
188 argptr += strlen(argptr);
189 sprintf (argptr, " idebus=%d", pciclock);
190 if (pciclock < 20 || pciclock > 66)
191 printk ("WARNING: IDE timing calculations will be incorrect\n");
192 }
193 }
194#endif
195#ifdef CONFIG_BLK_DEV_FD
196 fd_activate ();
197#endif
198#ifdef CONFIG_VT
199#if defined(CONFIG_VGA_CONSOLE)
200 screen_info = (struct screen_info) {
201 0, 25, /* orig-x, orig-y */
202 0, /* unused */
203 0, /* orig-video-page */
204 0, /* orig-video-mode */
205 80, /* orig-video-cols */
206 0,0,0, /* ega_ax, ega_bx, ega_cx */
207 25, /* orig-video-lines */
208 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
209 16 /* orig-video-points */
210 };
211#endif
212#endif
213
214#ifdef CONFIG_MTD
215 /*
216 * Support for MTD on Malta. Use the generic physmap driver
217 */
218 physmap_configure(0x1e000000, 0x400000, 4, NULL);
219 physmap_set_partitions(malta_mtd_partitions, number_partitions);
220#endif
221
222 mips_reboot_setup();
223
224 board_time_init = mips_time_init;
225 board_timer_setup = mips_timer_setup;
226 rtc_get_time = mips_rtc_get_time;
227
228 return 0;
229}
230
231early_initcall(malta_setup);
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