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authorDmitri Vorobiev <dmitri.vorobiev@gmail.com>2008-01-24 11:52:56 -0500
committerRalf Baechle <ralf@linux-mips.org>2008-01-29 05:15:05 -0500
commit750dc31c480e5062b526134f090a029afd7e17fd (patch)
tree605e2e9cb72232fbd50954fdaaf1bec2b8d0bb97 /arch/mips/mips-boards/malta/malta_setup.c
parentef7645cfe6f785de3bdc2ae6016924f46f614d61 (diff)
[MIPS] Malta: remaining bits of the board support code cleanup
This patch factors out the code, which handles the Bonito system controller. The case of not supporting the DMA coherency is handled separately to make the logic obvious. Besides, a couple of empty lines added to beautify the code even further. No functional changes introduced. Signed-off-by: Dmitri Vorobiev <dmitri.vorobiev@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards/malta/malta_setup.c')
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c80
1 files changed, 42 insertions, 38 deletions
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 541f4e76747f..2cd8f5734b36 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Carsten Langgaard, carstenl@mips.com 2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. 3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
4 * Copyright (C) Dmitri Vorobiev
4 * 5 *
5 * This program is free software; you can distribute it and/or modify it 6 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as 7 * under the terms of the GNU General Public License (Version 2) as
@@ -145,6 +146,41 @@ static void __init screen_info_setup(void)
145} 146}
146#endif 147#endif
147 148
149static void __init bonito_quirks_setup(void)
150{
151 char *argptr;
152
153 argptr = prom_getcmdline();
154 if (strstr(argptr, "debug")) {
155 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
156 printk(KERN_INFO "Enabled Bonito debug mode\n");
157 } else
158 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
159
160#ifdef CONFIG_DMA_COHERENT
161 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
162 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
163 printk(KERN_INFO "Enabled Bonito CPU coherency\n");
164
165 argptr = prom_getcmdline();
166 if (strstr(argptr, "iobcuncached")) {
167 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
168 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
169 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
170 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
171 printk(KERN_INFO "Disabled Bonito IOBC coherency\n");
172 } else {
173 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
174 BONITO_PCIMEMBASECFG |=
175 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
176 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
177 printk(KERN_INFO "Enabled Bonito IOBC coherency\n");
178 }
179 } else
180 panic("Hardware DMA cache coherency not supported");
181#endif
182}
183
148void __init plat_mem_setup(void) 184void __init plat_mem_setup(void)
149{ 185{
150 unsigned int i; 186 unsigned int i;
@@ -164,54 +200,22 @@ void __init plat_mem_setup(void)
164 kgdb_config(); 200 kgdb_config();
165#endif 201#endif
166 202
167 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
168 char *argptr;
169
170 argptr = prom_getcmdline();
171 if (strstr(argptr, "debug")) {
172 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
173 printk("Enabled Bonito debug mode\n");
174 }
175 else
176 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
177
178#ifdef CONFIG_DMA_COHERENT 203#ifdef CONFIG_DMA_COHERENT
179 if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { 204 if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
180 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
181 printk("Enabled Bonito CPU coherency\n");
182
183 argptr = prom_getcmdline();
184 if (strstr(argptr, "iobcuncached")) {
185 BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
186 BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
187 ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
188 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
189 printk("Disabled Bonito IOBC coherency\n");
190 }
191 else {
192 BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
193 BONITO_PCIMEMBASECFG |=
194 (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
195 BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
196 printk("Enabled Bonito IOBC coherency\n");
197 }
198 }
199 else
200 panic("Hardware DMA cache coherency not supported");
201
202#endif
203 }
204#ifdef CONFIG_DMA_COHERENT
205 else
206 panic("Hardware DMA cache coherency not supported"); 205 panic("Hardware DMA cache coherency not supported");
207#endif 206#endif
208 207
208 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
209 bonito_quirks_setup();
210
209#ifdef CONFIG_BLK_DEV_IDE 211#ifdef CONFIG_BLK_DEV_IDE
210 pci_clock_check(); 212 pci_clock_check();
211#endif 213#endif
214
212#ifdef CONFIG_BLK_DEV_FD 215#ifdef CONFIG_BLK_DEV_FD
213 fd_activate(); 216 fd_activate();
214#endif 217#endif
218
215#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 219#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE)
216 screen_info_setup(); 220 screen_info_setup();
217#endif 221#endif