[MIPS] Consolidate all variants of MIPS cp0 timer interrupt handlers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 5 insertions, 107 deletions

diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 075f9d46f40e..345de881013c 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -68,108 +68,6 @@ static void mips_perf_dispatch(void)
 }
 
 /*
- * Redeclare until I get around mopping the timer code insanity on MIPS.
- */
-extern int null_perf_irq(void);
-
-extern int (*perf_irq)(void);
-
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-static inline int handle_perf_irq (int r2)
-{
-        /*
-         * The performance counter overflow interrupt may be shared with the
-         * timer interrupt (cp0_perfcount_irq < 0). If it is and a
-         * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
-         * and we can't reliably determine if a counter interrupt has also
-         * happened (!r2) then don't check for a timer interrupt.
-         */
-        return (cp0_perfcount_irq < 0) &&
-                perf_irq() == IRQ_HANDLED &&
-                !r2;
-}
-
-irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
-{
-        int cpu = smp_processor_id();
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        /*
-         *  In an SMTC system, one Count/Compare set exists per VPE.
-         *  Which TC within a VPE gets the interrupt is essentially
-         *  random - we only know that it shouldn't be one with
-         *  IXMT set. Whichever TC gets the interrupt needs to
-         *  send special interprocessor interrupts to the other
-         *  TCs to make sure that they schedule, etc.
-         *
-         *  That code is specific to the SMTC kernel, not to
-         *  the a particular platform, so it's invoked from
-         *  the general MIPS timer_interrupt routine.
-         */
-
-        /*
-         * We could be here due to timer interrupt,
-         * perf counter overflow, or both.
-         */
-        (void) handle_perf_irq(1);
-
-        if (read_c0_cause() & (1 << 30)) {
-                /*
-                 * There are things we only want to do once per tick
-                 * in an "MP" system.   One TC of each VPE will take
-                 * the actual timer interrupt.  The others will get
-                 * timer broadcast IPIs. We use whoever it is that takes
-                 * the tick on VPE 0 to run the full timer_interrupt().
-                 */
-                if (cpu_data[cpu].vpe_id == 0) {
-                        timer_interrupt(irq, NULL);
-                } else {
-                        write_c0_compare(read_c0_count() +
-                                         (mips_hpt_frequency/HZ));
-                        local_timer_interrupt(irq, dev_id);
-                }
-                smtc_timer_broadcast();
-        }
-#else /* CONFIG_MIPS_MT_SMTC */
-        int r2 = cpu_has_mips_r2;
-
-        if (handle_perf_irq(r2))
-                goto out;
-
-        if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
-                goto out;
-
-        if (cpu == 0) {
-                /*
-                 * CPU 0 handles the global timer interrupt job and process
-                 * accounting resets count/compare registers to trigger next
-                 * timer int.
-                 */
-                timer_interrupt(irq, NULL);
-        } else {
-                /* Everyone else needs to reset the timer int here as
-                   ll_local_timer_interrupt doesn't */
-                /*
-                 * FIXME: need to cope with counter underflow.
-                 * More support needs to be added to kernel/time for
-                 * counter/timer interrupts on multiple CPU's
-                 */
-                write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
-
-                /*
-                 * Other CPUs should do profiling and process accounting
-                 */
-                local_timer_interrupt(irq, dev_id);
-        }
-out:
-#endif /* CONFIG_MIPS_MT_SMTC */
-        return IRQ_HANDLED;
-}
-
-/*
  * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
  */
 static unsigned int __init estimate_cpu_frequency(void)
@@ -246,7 +144,7 @@ void __init plat_time_init(void)
         mips_scroll_message();
 }
 
-irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
+static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
 {
         return perf_irq();
 }
@@ -257,8 +155,10 @@ static struct irqaction perf_irqaction = {
         .name = "performance",
 };
 
-void __init plat_perf_setup(struct irqaction *irq)
+void __init plat_perf_setup(void)
 {
+        struct irqaction *irq = &perf_irqaction;
+
         cp0_perfcount_irq = -1;
 
 #ifdef MSC01E_INT_BASE
@@ -297,8 +197,6 @@ void __init plat_timer_setup(struct irqaction *irq)
                 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
         }
 
-        /* we are using the cpu counter for timer interrupts */
-        irq->handler = mips_timer_interrupt;    /* we use our own handler */
 #ifdef CONFIG_MIPS_MT_SMTC
         setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
 #else
@@ -308,5 +206,5 @@ void __init plat_timer_setup(struct irqaction *irq)
         set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
 #endif
 
-        plat_perf_setup(&perf_irqaction);
+        plat_perf_setup();
 }