MIPS: Oprofile: Fixup the loose ends in the plumbing.

    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 17 insertions, 3 deletions

diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 2830f656fe2f..93f3bf2c2b22 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -75,16 +75,29 @@ static void mips_timer_dispatch (struct pt_regs *regs)
         do_IRQ (mips_cpu_timer_irq, regs);
 }
 
+extern int null_perf_irq(struct pt_regs *regs);
+
+extern int (*perf_irq)(struct pt_regs *regs);
+
 irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 {
+        int r2 = cpu_has_mips_r2;
         int cpu = smp_processor_id();
 
         if (cpu == 0) {
                 /*
-                 * CPU 0 handles the global timer interrupt job and process accounting
-                 * resets count/compare registers to trigger next timer int.
+                 * CPU 0 handles the global timer interrupt job and process
+                 * accounting resets count/compare registers to trigger next
+                 * timer int.
                  */
-                timer_interrupt(irq, dev_id, regs);
+                if (!r2 || (read_c0_cause() & (1 << 26)))
+                        if (perf_irq(regs))
+                                goto out;
+
+                /* we keep interrupt disabled all the time */
+                if (!r2 || (read_c0_cause() & (1 << 30)))
+                        timer_interrupt(irq, NULL, regs);
+
                 scroll_display_message();
         } else {
                 /* Everyone else needs to reset the timer int here as
@@ -101,6 +114,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
                 local_timer_interrupt (irq, dev_id, regs);
         }
 
+out:
         return IRQ_HANDLED;
 }