MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructions

MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and
BEQZALC instructions.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 7f373a2858b5..c115d969664b 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -623,6 +623,15 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
                                 dec_insn.pc_inc +
                                 dec_insn.next_pc_inc;
                 return 1;
+        case cbcond0_op:
+                if (!cpu_has_mips_r6)
+                        break;
+                if (insn.i_format.rt && !insn.i_format.rs)
+                        regs->regs[31] = regs->cp0_epc + 4;
+                *contpc = regs->cp0_epc + dec_insn.pc_inc +
+                        dec_insn.next_pc_inc;
+
+                return 1;
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
         case lwc2_op: /* This is bbit0 on Octeon */
                 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)