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authorRalf Baechle <ralf@linux-mips.org>2005-02-28 12:55:57 -0500
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:30:46 -0400
commit333d1f6794b341df11f286f5dca123c6dc64a770 (patch)
tree65218399e74b00d17e1b86b2086d781866028d85 /arch/mips/math-emu
parent0bd5d2e9ec8cc04a0225c590d35dd097e6b3a3f6 (diff)
Gross macro abuse. Get rid of gpreg_t, vaddr_t, REG_TO_VA and
VA_TO_REG. Who ever wrote this apparently did enjoy the C Puzzle Book. ISBN 0201604612, a little old but still fun reading for the next blackout ;) Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu')
-rw-r--r--arch/mips/math-emu/cp1emu.c48
-rw-r--r--arch/mips/math-emu/dsemul.c10
-rw-r--r--arch/mips/math-emu/dsemul.h10
3 files changed, 31 insertions, 37 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 99c550632d44..c70f25f5889e 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -196,7 +196,7 @@ static int isBranchInstr(mips_instruction * i)
196static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) 196static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
197{ 197{
198 mips_instruction ir; 198 mips_instruction ir;
199 vaddr_t emulpc, contpc; 199 void * emulpc, *contpc;
200 unsigned int cond; 200 unsigned int cond;
201 201
202 if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { 202 if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) {
@@ -221,12 +221,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
221 * Linux MIPS branch emulator operates on context, updating the 221 * Linux MIPS branch emulator operates on context, updating the
222 * cp0_epc. 222 * cp0_epc.
223 */ 223 */
224 emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */ 224 emulpc = (void *) (xcp->cp0_epc + 4); /* Snapshot emulation target */
225 225
226 if (__compute_return_epc(xcp)) { 226 if (__compute_return_epc(xcp)) {
227#ifdef CP1DBG 227#ifdef CP1DBG
228 printk("failed to emulate branch at %p\n", 228 printk("failed to emulate branch at %p\n",
229 REG_TO_VA(xcp->cp0_epc)); 229 (void *) (xcp->cp0_epc));
230#endif 230#endif
231 return SIGILL; 231 return SIGILL;
232 } 232 }
@@ -235,13 +235,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
235 return SIGBUS; 235 return SIGBUS;
236 } 236 }
237 /* __compute_return_epc() will have updated cp0_epc */ 237 /* __compute_return_epc() will have updated cp0_epc */
238 contpc = REG_TO_VA xcp->cp0_epc; 238 contpc = (void *) xcp->cp0_epc;
239 /* In order not to confuse ptrace() et al, tweak context */ 239 /* In order not to confuse ptrace() et al, tweak context */
240 xcp->cp0_epc = VA_TO_REG emulpc - 4; 240 xcp->cp0_epc = (unsigned long) emulpc - 4;
241 } 241 } else {
242 else { 242 emulpc = (void *) xcp->cp0_epc;
243 emulpc = REG_TO_VA xcp->cp0_epc; 243 contpc = (void *) (xcp->cp0_epc + 4);
244 contpc = REG_TO_VA(xcp->cp0_epc + 4);
245 } 244 }
246 245
247 emul: 246 emul:
@@ -249,7 +248,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
249 switch (MIPSInst_OPCODE(ir)) { 248 switch (MIPSInst_OPCODE(ir)) {
250#ifndef SINGLE_ONLY_FPU 249#ifndef SINGLE_ONLY_FPU
251 case ldc1_op:{ 250 case ldc1_op:{
252 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 251 u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
253 MIPSInst_SIMM(ir)); 252 MIPSInst_SIMM(ir));
254 u64 val; 253 u64 val;
255 254
@@ -263,7 +262,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
263 } 262 }
264 263
265 case sdc1_op:{ 264 case sdc1_op:{
266 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 265 u64 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
267 MIPSInst_SIMM(ir)); 266 MIPSInst_SIMM(ir));
268 u64 val; 267 u64 val;
269 268
@@ -278,7 +277,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
278#endif 277#endif
279 278
280 case lwc1_op:{ 279 case lwc1_op:{
281 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 280 u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
282 MIPSInst_SIMM(ir)); 281 MIPSInst_SIMM(ir));
283 u32 val; 282 u32 val;
284 283
@@ -298,7 +297,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
298 } 297 }
299 298
300 case swc1_op:{ 299 case swc1_op:{
301 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + 300 u32 *va = (void *) (xcp->regs[MIPSInst_RS(ir)] +
302 MIPSInst_SIMM(ir)); 301 MIPSInst_SIMM(ir));
303 u32 val; 302 u32 val;
304 303
@@ -371,7 +370,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
371 value = ctx->fcr31; 370 value = ctx->fcr31;
372#ifdef CSRTRACE 371#ifdef CSRTRACE
373 printk("%p gpr[%d]<-csr=%08x\n", 372 printk("%p gpr[%d]<-csr=%08x\n",
374 REG_TO_VA(xcp->cp0_epc), 373 (void *) (xcp->cp0_epc),
375 MIPSInst_RT(ir), value); 374 MIPSInst_RT(ir), value);
376#endif 375#endif
377 } 376 }
@@ -398,7 +397,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
398 if (MIPSInst_RD(ir) == FPCREG_CSR) { 397 if (MIPSInst_RD(ir) == FPCREG_CSR) {
399#ifdef CSRTRACE 398#ifdef CSRTRACE
400 printk("%p gpr[%d]->csr=%08x\n", 399 printk("%p gpr[%d]->csr=%08x\n",
401 REG_TO_VA(xcp->cp0_epc), 400 (void *) (xcp->cp0_epc),
402 MIPSInst_RT(ir), value); 401 MIPSInst_RT(ir), value);
403#endif 402#endif
404 ctx->fcr31 = value; 403 ctx->fcr31 = value;
@@ -445,12 +444,12 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
445 * instruction 444 * instruction
446 */ 445 */
447 xcp->cp0_epc += 4; 446 xcp->cp0_epc += 4;
448 contpc = REG_TO_VA 447 contpc = (void *)
449 (xcp->cp0_epc + 448 (xcp->cp0_epc +
450 (MIPSInst_SIMM(ir) << 2)); 449 (MIPSInst_SIMM(ir) << 2));
451 450
452 if (get_user(ir, (mips_instruction *) 451 if (get_user(ir, (mips_instruction *)
453 REG_TO_VA xcp->cp0_epc)) { 452 (void *) xcp->cp0_epc)) {
454 fpuemuprivate.stats.errors++; 453 fpuemuprivate.stats.errors++;
455 return SIGBUS; 454 return SIGBUS;
456 } 455 }
@@ -480,7 +479,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
480 * Single step the non-cp1 479 * Single step the non-cp1
481 * instruction in the dslot 480 * instruction in the dslot
482 */ 481 */
483 return mips_dsemul(xcp, ir, VA_TO_REG contpc); 482 return mips_dsemul(xcp, ir, (unsigned long) contpc);
484 } 483 }
485 else { 484 else {
486 /* branch not taken */ 485 /* branch not taken */
@@ -539,8 +538,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
539 } 538 }
540 539
541 /* we did it !! */ 540 /* we did it !! */
542 xcp->cp0_epc = VA_TO_REG(contpc); 541 xcp->cp0_epc = (unsigned long) contpc;
543 xcp->cp0_cause &= ~CAUSEF_BD; 542 xcp->cp0_cause &= ~CAUSEF_BD;
543
544 return 0; 544 return 0;
545} 545}
546 546
@@ -628,7 +628,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
628 628
629 switch (MIPSInst_FUNC(ir)) { 629 switch (MIPSInst_FUNC(ir)) {
630 case lwxc1_op: 630 case lwxc1_op:
631 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 631 va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
632 xcp->regs[MIPSInst_FT(ir)]); 632 xcp->regs[MIPSInst_FT(ir)]);
633 633
634 fpuemuprivate.stats.loads++; 634 fpuemuprivate.stats.loads++;
@@ -648,7 +648,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
648 break; 648 break;
649 649
650 case swxc1_op: 650 case swxc1_op:
651 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 651 va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
652 xcp->regs[MIPSInst_FT(ir)]); 652 xcp->regs[MIPSInst_FT(ir)]);
653 653
654 fpuemuprivate.stats.stores++; 654 fpuemuprivate.stats.stores++;
@@ -724,7 +724,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
724 724
725 switch (MIPSInst_FUNC(ir)) { 725 switch (MIPSInst_FUNC(ir)) {
726 case ldxc1_op: 726 case ldxc1_op:
727 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 727 va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
728 xcp->regs[MIPSInst_FT(ir)]); 728 xcp->regs[MIPSInst_FT(ir)]);
729 729
730 fpuemuprivate.stats.loads++; 730 fpuemuprivate.stats.loads++;
@@ -736,7 +736,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
736 break; 736 break;
737 737
738 case sdxc1_op: 738 case sdxc1_op:
739 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + 739 va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
740 xcp->regs[MIPSInst_FT(ir)]); 740 xcp->regs[MIPSInst_FT(ir)]);
741 741
742 fpuemuprivate.stats.stores++; 742 fpuemuprivate.stats.stores++;
@@ -1282,7 +1282,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1282int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, 1282int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
1283 struct mips_fpu_soft_struct *ctx) 1283 struct mips_fpu_soft_struct *ctx)
1284{ 1284{
1285 gpreg_t oldepc, prevepc; 1285 unsigned long oldepc, prevepc;
1286 mips_instruction insn; 1286 mips_instruction insn;
1287 int sig = 0; 1287 int sig = 0;
1288 1288
diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c
index 688be60c5385..d48bb62495bf 100644
--- a/arch/mips/math-emu/dsemul.c
+++ b/arch/mips/math-emu/dsemul.c
@@ -49,10 +49,10 @@ struct emuframe {
49 mips_instruction emul; 49 mips_instruction emul;
50 mips_instruction badinst; 50 mips_instruction badinst;
51 mips_instruction cookie; 51 mips_instruction cookie;
52 gpreg_t epc; 52 unsigned long epc;
53}; 53};
54 54
55int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc) 55int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc)
56{ 56{
57 extern asmlinkage void handle_dsemulret(void); 57 extern asmlinkage void handle_dsemulret(void);
58 mips_instruction *dsemul_insns; 58 mips_instruction *dsemul_insns;
@@ -88,7 +88,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
88 */ 88 */
89 89
90 /* Ensure that the two instructions are in the same cache line */ 90 /* Ensure that the two instructions are in the same cache line */
91 dsemul_insns = (mips_instruction *) REG_TO_VA ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7); 91 dsemul_insns = (mips_instruction *) ((regs->regs[29] - sizeof(struct emuframe)) & ~0x7);
92 fr = (struct emuframe *) dsemul_insns; 92 fr = (struct emuframe *) dsemul_insns;
93 93
94 /* Verify that the stack pointer is not competely insane */ 94 /* Verify that the stack pointer is not competely insane */
@@ -105,7 +105,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
105 return SIGBUS; 105 return SIGBUS;
106 } 106 }
107 107
108 regs->cp0_epc = VA_TO_REG & fr->emul; 108 regs->cp0_epc = (unsigned long) &fr->emul;
109 109
110 flush_cache_sigtramp((unsigned long)&fr->badinst); 110 flush_cache_sigtramp((unsigned long)&fr->badinst);
111 111
@@ -115,7 +115,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc)
115int do_dsemulret(struct pt_regs *xcp) 115int do_dsemulret(struct pt_regs *xcp)
116{ 116{
117 struct emuframe *fr; 117 struct emuframe *fr;
118 gpreg_t epc; 118 unsigned long epc;
119 u32 insn, cookie; 119 u32 insn, cookie;
120 int err = 0; 120 int err = 0;
121 121
diff --git a/arch/mips/math-emu/dsemul.h b/arch/mips/math-emu/dsemul.h
index dbd85f95268d..091f0e76730f 100644
--- a/arch/mips/math-emu/dsemul.h
+++ b/arch/mips/math-emu/dsemul.h
@@ -1,11 +1,5 @@
1typedef long gpreg_t; 1extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc);
2typedef void *vaddr_t; 2extern int do_dsemulret(struct pt_regs *xcp);
3
4#define REG_TO_VA (vaddr_t)
5#define VA_TO_REG (gpreg_t)
6
7int mips_dsemul(struct pt_regs *regs, mips_instruction ir, gpreg_t cpc);
8int do_dsemulret(struct pt_regs *xcp);
9 3
10/* Instruction which will always cause an address error */ 4/* Instruction which will always cause an address error */
11#define AdELOAD 0x8c000001 /* lw $0,1($0) */ 5#define AdELOAD 0x8c000001 /* lw $0,1($0) */