diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2005-05-11 08:02:48 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:31:14 -0400 |
commit | 4a99d1e25b98c239d6e746af6f79679c413fb712 (patch) | |
tree | 4a68322a855668b767e211cab8804fd6d01e4097 /arch/mips/math-emu/cp1emu.c | |
parent | baee502ce2048aad5ec56acd24c950083a4697e7 (diff) |
Now that a struct is the only member left in struct
mips_fpu_emulator_stats cleanup that unnecessary nesting of structs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu/cp1emu.c')
-rw-r--r-- | arch/mips/math-emu/cp1emu.c | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 6fed6ce43c4e..190bdf9921be 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c | |||
@@ -70,7 +70,7 @@ static int fpux_emu(struct pt_regs *, | |||
70 | 70 | ||
71 | /* Further private data for which no space exists in mips_fpu_soft_struct */ | 71 | /* Further private data for which no space exists in mips_fpu_soft_struct */ |
72 | 72 | ||
73 | struct mips_fpu_emulator_private fpuemuprivate; | 73 | struct mips_fpu_emulator_stats fpuemustats; |
74 | 74 | ||
75 | /* Control registers */ | 75 | /* Control registers */ |
76 | 76 | ||
@@ -210,7 +210,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
210 | unsigned int cond; | 210 | unsigned int cond; |
211 | 211 | ||
212 | if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { | 212 | if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { |
213 | fpuemuprivate.stats.errors++; | 213 | fpuemustats.errors++; |
214 | return SIGBUS; | 214 | return SIGBUS; |
215 | } | 215 | } |
216 | 216 | ||
@@ -241,7 +241,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
241 | return SIGILL; | 241 | return SIGILL; |
242 | } | 242 | } |
243 | if (get_user(ir, (mips_instruction *) emulpc)) { | 243 | if (get_user(ir, (mips_instruction *) emulpc)) { |
244 | fpuemuprivate.stats.errors++; | 244 | fpuemustats.errors++; |
245 | return SIGBUS; | 245 | return SIGBUS; |
246 | } | 246 | } |
247 | /* __compute_return_epc() will have updated cp0_epc */ | 247 | /* __compute_return_epc() will have updated cp0_epc */ |
@@ -254,7 +254,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
254 | } | 254 | } |
255 | 255 | ||
256 | emul: | 256 | emul: |
257 | fpuemuprivate.stats.emulated++; | 257 | fpuemustats.emulated++; |
258 | switch (MIPSInst_OPCODE(ir)) { | 258 | switch (MIPSInst_OPCODE(ir)) { |
259 | #ifndef SINGLE_ONLY_FPU | 259 | #ifndef SINGLE_ONLY_FPU |
260 | case ldc1_op:{ | 260 | case ldc1_op:{ |
@@ -262,9 +262,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
262 | MIPSInst_SIMM(ir)); | 262 | MIPSInst_SIMM(ir)); |
263 | u64 val; | 263 | u64 val; |
264 | 264 | ||
265 | fpuemuprivate.stats.loads++; | 265 | fpuemustats.loads++; |
266 | if (get_user(val, va)) { | 266 | if (get_user(val, va)) { |
267 | fpuemuprivate.stats.errors++; | 267 | fpuemustats.errors++; |
268 | return SIGBUS; | 268 | return SIGBUS; |
269 | } | 269 | } |
270 | DITOREG(val, MIPSInst_RT(ir)); | 270 | DITOREG(val, MIPSInst_RT(ir)); |
@@ -276,10 +276,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
276 | MIPSInst_SIMM(ir)); | 276 | MIPSInst_SIMM(ir)); |
277 | u64 val; | 277 | u64 val; |
278 | 278 | ||
279 | fpuemuprivate.stats.stores++; | 279 | fpuemustats.stores++; |
280 | DIFROMREG(val, MIPSInst_RT(ir)); | 280 | DIFROMREG(val, MIPSInst_RT(ir)); |
281 | if (put_user(val, va)) { | 281 | if (put_user(val, va)) { |
282 | fpuemuprivate.stats.errors++; | 282 | fpuemustats.errors++; |
283 | return SIGBUS; | 283 | return SIGBUS; |
284 | } | 284 | } |
285 | break; | 285 | break; |
@@ -291,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
291 | MIPSInst_SIMM(ir)); | 291 | MIPSInst_SIMM(ir)); |
292 | u32 val; | 292 | u32 val; |
293 | 293 | ||
294 | fpuemuprivate.stats.loads++; | 294 | fpuemustats.loads++; |
295 | if (get_user(val, va)) { | 295 | if (get_user(val, va)) { |
296 | fpuemuprivate.stats.errors++; | 296 | fpuemustats.errors++; |
297 | return SIGBUS; | 297 | return SIGBUS; |
298 | } | 298 | } |
299 | #ifdef SINGLE_ONLY_FPU | 299 | #ifdef SINGLE_ONLY_FPU |
@@ -311,7 +311,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
311 | MIPSInst_SIMM(ir)); | 311 | MIPSInst_SIMM(ir)); |
312 | u32 val; | 312 | u32 val; |
313 | 313 | ||
314 | fpuemuprivate.stats.stores++; | 314 | fpuemustats.stores++; |
315 | #ifdef SINGLE_ONLY_FPU | 315 | #ifdef SINGLE_ONLY_FPU |
316 | if (MIPSInst_RT(ir) & 1) { | 316 | if (MIPSInst_RT(ir) & 1) { |
317 | /* illegal register in single-float mode */ | 317 | /* illegal register in single-float mode */ |
@@ -320,7 +320,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
320 | #endif | 320 | #endif |
321 | SIFROMREG(val, MIPSInst_RT(ir)); | 321 | SIFROMREG(val, MIPSInst_RT(ir)); |
322 | if (put_user(val, va)) { | 322 | if (put_user(val, va)) { |
323 | fpuemuprivate.stats.errors++; | 323 | fpuemustats.errors++; |
324 | return SIGBUS; | 324 | return SIGBUS; |
325 | } | 325 | } |
326 | break; | 326 | break; |
@@ -460,7 +460,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) | |||
460 | 460 | ||
461 | if (get_user(ir, (mips_instruction *) | 461 | if (get_user(ir, (mips_instruction *) |
462 | (void *) xcp->cp0_epc)) { | 462 | (void *) xcp->cp0_epc)) { |
463 | fpuemuprivate.stats.errors++; | 463 | fpuemustats.errors++; |
464 | return SIGBUS; | 464 | return SIGBUS; |
465 | } | 465 | } |
466 | 466 | ||
@@ -626,7 +626,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, | |||
626 | { | 626 | { |
627 | unsigned rcsr = 0; /* resulting csr */ | 627 | unsigned rcsr = 0; /* resulting csr */ |
628 | 628 | ||
629 | fpuemuprivate.stats.cp1xops++; | 629 | fpuemustats.cp1xops++; |
630 | 630 | ||
631 | switch (MIPSInst_FMA_FFMT(ir)) { | 631 | switch (MIPSInst_FMA_FFMT(ir)) { |
632 | case s_fmt:{ /* 0 */ | 632 | case s_fmt:{ /* 0 */ |
@@ -641,9 +641,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, | |||
641 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + | 641 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + |
642 | xcp->regs[MIPSInst_FT(ir)]); | 642 | xcp->regs[MIPSInst_FT(ir)]); |
643 | 643 | ||
644 | fpuemuprivate.stats.loads++; | 644 | fpuemustats.loads++; |
645 | if (get_user(val, va)) { | 645 | if (get_user(val, va)) { |
646 | fpuemuprivate.stats.errors++; | 646 | fpuemustats.errors++; |
647 | return SIGBUS; | 647 | return SIGBUS; |
648 | } | 648 | } |
649 | #ifdef SINGLE_ONLY_FPU | 649 | #ifdef SINGLE_ONLY_FPU |
@@ -661,7 +661,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, | |||
661 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + | 661 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + |
662 | xcp->regs[MIPSInst_FT(ir)]); | 662 | xcp->regs[MIPSInst_FT(ir)]); |
663 | 663 | ||
664 | fpuemuprivate.stats.stores++; | 664 | fpuemustats.stores++; |
665 | #ifdef SINGLE_ONLY_FPU | 665 | #ifdef SINGLE_ONLY_FPU |
666 | if (MIPSInst_FS(ir) & 1) { | 666 | if (MIPSInst_FS(ir) & 1) { |
667 | /* illegal register in single-float | 667 | /* illegal register in single-float |
@@ -673,7 +673,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, | |||
673 | 673 | ||
674 | SIFROMREG(val, MIPSInst_FS(ir)); | 674 | SIFROMREG(val, MIPSInst_FS(ir)); |
675 | if (put_user(val, va)) { | 675 | if (put_user(val, va)) { |
676 | fpuemuprivate.stats.errors++; | 676 | fpuemustats.errors++; |
677 | return SIGBUS; | 677 | return SIGBUS; |
678 | } | 678 | } |
679 | break; | 679 | break; |
@@ -735,9 +735,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, | |||
735 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + | 735 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + |
736 | xcp->regs[MIPSInst_FT(ir)]); | 736 | xcp->regs[MIPSInst_FT(ir)]); |
737 | 737 | ||
738 | fpuemuprivate.stats.loads++; | 738 | fpuemustats.loads++; |
739 | if (get_user(val, va)) { | 739 | if (get_user(val, va)) { |
740 | fpuemuprivate.stats.errors++; | 740 | fpuemustats.errors++; |
741 | return SIGBUS; | 741 | return SIGBUS; |
742 | } | 742 | } |
743 | DITOREG(val, MIPSInst_FD(ir)); | 743 | DITOREG(val, MIPSInst_FD(ir)); |
@@ -747,10 +747,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, | |||
747 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + | 747 | va = (void *) (xcp->regs[MIPSInst_FR(ir)] + |
748 | xcp->regs[MIPSInst_FT(ir)]); | 748 | xcp->regs[MIPSInst_FT(ir)]); |
749 | 749 | ||
750 | fpuemuprivate.stats.stores++; | 750 | fpuemustats.stores++; |
751 | DIFROMREG(val, MIPSInst_FS(ir)); | 751 | DIFROMREG(val, MIPSInst_FS(ir)); |
752 | if (put_user(val, va)) { | 752 | if (put_user(val, va)) { |
753 | fpuemuprivate.stats.errors++; | 753 | fpuemustats.errors++; |
754 | return SIGBUS; | 754 | return SIGBUS; |
755 | } | 755 | } |
756 | break; | 756 | break; |
@@ -818,7 +818,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, | |||
818 | #endif | 818 | #endif |
819 | } rv; /* resulting value */ | 819 | } rv; /* resulting value */ |
820 | 820 | ||
821 | fpuemuprivate.stats.cp1ops++; | 821 | fpuemustats.cp1ops++; |
822 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { | 822 | switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { |
823 | case s_fmt:{ /* 0 */ | 823 | case s_fmt:{ /* 0 */ |
824 | union { | 824 | union { |
@@ -1299,7 +1299,7 @@ int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp, | |||
1299 | prevepc = xcp->cp0_epc; | 1299 | prevepc = xcp->cp0_epc; |
1300 | 1300 | ||
1301 | if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { | 1301 | if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) { |
1302 | fpuemuprivate.stats.errors++; | 1302 | fpuemustats.errors++; |
1303 | return SIGBUS; | 1303 | return SIGBUS; |
1304 | } | 1304 | } |
1305 | if (insn == 0) | 1305 | if (insn == 0) |