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authorRalf Baechle <ralf@linux-mips.org>2005-10-23 10:05:47 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:52 -0400
commit4b724efdde0287d7ba616bd2badc63fca414f978 (patch)
tree9c30ecd163d782a4fff8542b557d8811c3a4ef3e /arch/mips/math-emu/cp1emu.c
parent3fccc0150e720ff344b5f9c5f8dd23778139018e (diff)
Get rid of SINGLE_ONLY_FPU. Linux does not support half FPU other than
by emulation of a full FPU. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/math-emu/cp1emu.c')
-rw-r--r--arch/mips/math-emu/cp1emu.c70
1 files changed, 8 insertions, 62 deletions
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index c4a7853c5714..aa5818a0d884 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -256,7 +256,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
256 emul: 256 emul:
257 fpuemustats.emulated++; 257 fpuemustats.emulated++;
258 switch (MIPSInst_OPCODE(ir)) { 258 switch (MIPSInst_OPCODE(ir)) {
259#ifndef SINGLE_ONLY_FPU
260 case ldc1_op:{ 259 case ldc1_op:{
261 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + 260 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
262 MIPSInst_SIMM(ir)); 261 MIPSInst_SIMM(ir));
@@ -284,7 +283,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
284 } 283 }
285 break; 284 break;
286 } 285 }
287#endif
288 286
289 case lwc1_op:{ 287 case lwc1_op:{
290 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] + 288 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
@@ -296,12 +294,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
296 fpuemustats.errors++; 294 fpuemustats.errors++;
297 return SIGBUS; 295 return SIGBUS;
298 } 296 }
299#ifdef SINGLE_ONLY_FPU
300 if (MIPSInst_RT(ir) & 1) {
301 /* illegal register in single-float mode */
302 return SIGILL;
303 }
304#endif
305 SITOREG(val, MIPSInst_RT(ir)); 297 SITOREG(val, MIPSInst_RT(ir));
306 break; 298 break;
307 } 299 }
@@ -312,12 +304,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
312 u32 val; 304 u32 val;
313 305
314 fpuemustats.stores++; 306 fpuemustats.stores++;
315#ifdef SINGLE_ONLY_FPU
316 if (MIPSInst_RT(ir) & 1) {
317 /* illegal register in single-float mode */
318 return SIGILL;
319 }
320#endif
321 SIFROMREG(val, MIPSInst_RT(ir)); 307 SIFROMREG(val, MIPSInst_RT(ir));
322 if (put_user(val, va)) { 308 if (put_user(val, va)) {
323 fpuemustats.errors++; 309 fpuemustats.errors++;
@@ -329,7 +315,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
329 case cop1_op: 315 case cop1_op:
330 switch (MIPSInst_RS(ir)) { 316 switch (MIPSInst_RS(ir)) {
331 317
332#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 318#if defined(__mips64)
333 case dmfc_op: 319 case dmfc_op:
334 /* copregister fs -> gpr[rt] */ 320 /* copregister fs -> gpr[rt] */
335 if (MIPSInst_RT(ir) != 0) { 321 if (MIPSInst_RT(ir) != 0) {
@@ -346,12 +332,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
346 332
347 case mfc_op: 333 case mfc_op:
348 /* copregister rd -> gpr[rt] */ 334 /* copregister rd -> gpr[rt] */
349#ifdef SINGLE_ONLY_FPU
350 if (MIPSInst_RD(ir) & 1) {
351 /* illegal register in single-float mode */
352 return SIGILL;
353 }
354#endif
355 if (MIPSInst_RT(ir) != 0) { 335 if (MIPSInst_RT(ir) != 0) {
356 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], 336 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
357 MIPSInst_RD(ir)); 337 MIPSInst_RD(ir));
@@ -360,12 +340,6 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
360 340
361 case mtc_op: 341 case mtc_op:
362 /* copregister rd <- rt */ 342 /* copregister rd <- rt */
363#ifdef SINGLE_ONLY_FPU
364 if (MIPSInst_RD(ir) & 1) {
365 /* illegal register in single-float mode */
366 return SIGILL;
367 }
368#endif
369 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); 343 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
370 break; 344 break;
371 345
@@ -467,7 +441,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx)
467 switch (MIPSInst_OPCODE(ir)) { 441 switch (MIPSInst_OPCODE(ir)) {
468 case lwc1_op: 442 case lwc1_op:
469 case swc1_op: 443 case swc1_op:
470#if (__mips >= 2 || defined(__mips64)) && !defined(SINGLE_ONLY_FPU) 444#if (__mips >= 2 || defined(__mips64))
471 case ldc1_op: 445 case ldc1_op:
472 case sdc1_op: 446 case sdc1_op:
473#endif 447#endif
@@ -646,14 +620,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
646 fpuemustats.errors++; 620 fpuemustats.errors++;
647 return SIGBUS; 621 return SIGBUS;
648 } 622 }
649#ifdef SINGLE_ONLY_FPU
650 if (MIPSInst_FD(ir) & 1) {
651 /* illegal register in single-float
652 * mode
653 */
654 return SIGILL;
655 }
656#endif
657 SITOREG(val, MIPSInst_FD(ir)); 623 SITOREG(val, MIPSInst_FD(ir));
658 break; 624 break;
659 625
@@ -662,14 +628,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
662 xcp->regs[MIPSInst_FT(ir)]); 628 xcp->regs[MIPSInst_FT(ir)]);
663 629
664 fpuemustats.stores++; 630 fpuemustats.stores++;
665#ifdef SINGLE_ONLY_FPU
666 if (MIPSInst_FS(ir) & 1) {
667 /* illegal register in single-float
668 * mode
669 */
670 return SIGILL;
671 }
672#endif
673 631
674 SIFROMREG(val, MIPSInst_FS(ir)); 632 SIFROMREG(val, MIPSInst_FS(ir));
675 if (put_user(val, va)) { 633 if (put_user(val, va)) {
@@ -723,7 +681,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
723 break; 681 break;
724 } 682 }
725 683
726#ifndef SINGLE_ONLY_FPU
727 case d_fmt:{ /* 1 */ 684 case d_fmt:{ /* 1 */
728 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp); 685 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
729 ieee754dp fd, fr, fs, ft; 686 ieee754dp fd, fr, fs, ft;
@@ -781,7 +738,6 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
781 } 738 }
782 break; 739 break;
783 } 740 }
784#endif
785 741
786 case 0x7: /* 7 */ 742 case 0x7: /* 7 */
787 if (MIPSInst_FUNC(ir) != pfetch_op) { 743 if (MIPSInst_FUNC(ir) != pfetch_op) {
@@ -921,9 +877,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
921 case fcvts_op: 877 case fcvts_op:
922 return SIGILL; /* not defined */ 878 return SIGILL; /* not defined */
923 case fcvtd_op:{ 879 case fcvtd_op:{
924#ifdef SINGLE_ONLY_FPU
925 return SIGILL; /* not defined */
926#else
927 ieee754sp fs; 880 ieee754sp fs;
928 881
929 SPFROMREG(fs, MIPSInst_FS(ir)); 882 SPFROMREG(fs, MIPSInst_FS(ir));
@@ -931,7 +884,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
931 rfmt = d_fmt; 884 rfmt = d_fmt;
932 goto copcsr; 885 goto copcsr;
933 } 886 }
934#endif
935 case fcvtw_op:{ 887 case fcvtw_op:{
936 ieee754sp fs; 888 ieee754sp fs;
937 889
@@ -958,7 +910,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
958 } 910 }
959#endif /* __mips >= 2 */ 911#endif /* __mips >= 2 */
960 912
961#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 913#if defined(__mips64)
962 case fcvtl_op:{ 914 case fcvtl_op:{
963 ieee754sp fs; 915 ieee754sp fs;
964 916
@@ -982,7 +934,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
982 rfmt = l_fmt; 934 rfmt = l_fmt;
983 goto copcsr; 935 goto copcsr;
984 } 936 }
985#endif /* defined(__mips64) && !fpu(single) */ 937#endif /* defined(__mips64) */
986 938
987 default: 939 default:
988 if (MIPSInst_FUNC(ir) >= fcmp_op) { 940 if (MIPSInst_FUNC(ir) >= fcmp_op) {
@@ -1009,7 +961,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1009 break; 961 break;
1010 } 962 }
1011 963
1012#ifndef SINGLE_ONLY_FPU
1013 case d_fmt:{ 964 case d_fmt:{
1014 union { 965 union {
1015 ieee754dp(*b) (ieee754dp, ieee754dp); 966 ieee754dp(*b) (ieee754dp, ieee754dp);
@@ -1133,7 +1084,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1133 } 1084 }
1134#endif 1085#endif
1135 1086
1136#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1087#if defined(__mips64)
1137 case fcvtl_op:{ 1088 case fcvtl_op:{
1138 ieee754dp fs; 1089 ieee754dp fs;
1139 1090
@@ -1157,7 +1108,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1157 rfmt = l_fmt; 1108 rfmt = l_fmt;
1158 goto copcsr; 1109 goto copcsr;
1159 } 1110 }
1160#endif /* __mips >= 3 && !fpu(single) */ 1111#endif /* __mips >= 3 */
1161 1112
1162 default: 1113 default:
1163 if (MIPSInst_FUNC(ir) >= fcmp_op) { 1114 if (MIPSInst_FUNC(ir) >= fcmp_op) {
@@ -1185,7 +1136,6 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1185 } 1136 }
1186 break; 1137 break;
1187 } 1138 }
1188#endif /* ifndef SINGLE_ONLY_FPU */
1189 1139
1190 case w_fmt:{ 1140 case w_fmt:{
1191 ieee754sp fs; 1141 ieee754sp fs;
@@ -1197,21 +1147,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1197 rv.s = ieee754sp_fint(fs.bits); 1147 rv.s = ieee754sp_fint(fs.bits);
1198 rfmt = s_fmt; 1148 rfmt = s_fmt;
1199 goto copcsr; 1149 goto copcsr;
1200#ifndef SINGLE_ONLY_FPU
1201 case fcvtd_op: 1150 case fcvtd_op:
1202 /* convert word to double precision real */ 1151 /* convert word to double precision real */
1203 SPFROMREG(fs, MIPSInst_FS(ir)); 1152 SPFROMREG(fs, MIPSInst_FS(ir));
1204 rv.d = ieee754dp_fint(fs.bits); 1153 rv.d = ieee754dp_fint(fs.bits);
1205 rfmt = d_fmt; 1154 rfmt = d_fmt;
1206 goto copcsr; 1155 goto copcsr;
1207#endif
1208 default: 1156 default:
1209 return SIGILL; 1157 return SIGILL;
1210 } 1158 }
1211 break; 1159 break;
1212 } 1160 }
1213 1161
1214#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1162#if defined(__mips64)
1215 case l_fmt:{ 1163 case l_fmt:{
1216 switch (MIPSInst_FUNC(ir)) { 1164 switch (MIPSInst_FUNC(ir)) {
1217 case fcvts_op: 1165 case fcvts_op:
@@ -1264,18 +1212,16 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx,
1264 ctx->fcr31 &= ~cond; 1212 ctx->fcr31 &= ~cond;
1265 break; 1213 break;
1266 } 1214 }
1267#ifndef SINGLE_ONLY_FPU
1268 case d_fmt: 1215 case d_fmt:
1269 DPTOREG(rv.d, MIPSInst_FD(ir)); 1216 DPTOREG(rv.d, MIPSInst_FD(ir));
1270 break; 1217 break;
1271#endif
1272 case s_fmt: 1218 case s_fmt:
1273 SPTOREG(rv.s, MIPSInst_FD(ir)); 1219 SPTOREG(rv.s, MIPSInst_FD(ir));
1274 break; 1220 break;
1275 case w_fmt: 1221 case w_fmt:
1276 SITOREG(rv.w, MIPSInst_FD(ir)); 1222 SITOREG(rv.w, MIPSInst_FD(ir));
1277 break; 1223 break;
1278#if defined(__mips64) && !defined(SINGLE_ONLY_FPU) 1224#if defined(__mips64)
1279 case l_fmt: 1225 case l_fmt:
1280 DITOREG(rv.l, MIPSInst_FD(ir)); 1226 DITOREG(rv.l, MIPSInst_FD(ir));
1281 break; 1227 break;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 16:35:10 -0500