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authorHuacai Chen <chenhc@lemote.com>2014-06-25 23:41:30 -0400
committerRalf Baechle <ralf@linux-mips.org>2014-07-30 15:47:00 -0400
commite7841be50fe2b8751a51a068b8cdcdcb6611e354 (patch)
treed0ffedc83975c17cfa3357ebcb806a2fa86d3566 /arch/mips/loongson
parent1ff1ad6bc2c63f219cbc00dcdd35dcf36a7d6fe4 (diff)
MIPS: Add Loongson-3B support
Loongson-3B is a 8-cores processor. In general it looks like there are two Loongson-3A integrated in one chip: 8 cores are separated into two groups (two NUMA node), each node has its own local memory. Of course there are some differences between one Loongson-3B and two Loongson-3A. E.g., the base addresses of IPI registers of each node are not the same; Loongson-3A use ChipConfig register to enable/disable clock, but Loongson-3B use FreqControl register instead. There are two revision of Loongson-3B, the first revision is called as Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the second revision is called as Loongson-3B1500, whose frequency is 1.5GHz and has a PRid 0x6307. Both revisions has a bug that clock cannot be disabled at runtime, but this will be fixed in future. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7188/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/loongson')
-rw-r--r--arch/mips/loongson/common/env.c31
-rw-r--r--arch/mips/loongson/loongson-3/irq.c26
-rw-r--r--arch/mips/loongson/loongson-3/smp.c387
-rw-r--r--arch/mips/loongson/loongson-3/smp.h37
4 files changed, 359 insertions, 122 deletions
diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index 33a13b9e436c..f15228550a22 100644
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -28,6 +28,10 @@ struct efi_memory_map_loongson *loongson_memmap;
28struct loongson_system_configuration loongson_sysconf; 28struct loongson_system_configuration loongson_sysconf;
29 29
30u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180}; 30u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
31u64 loongson_freqctrl[MAX_PACKAGES];
32
33unsigned long long smp_group[4];
34int cpuhotplug_workaround = 0;
31 35
32#define parse_even_earlier(res, option, p) \ 36#define parse_even_earlier(res, option, p) \
33do { \ 37do { \
@@ -82,10 +86,32 @@ void __init prom_init_env(void)
82 if (ecpu->cputype == Loongson_3A) { 86 if (ecpu->cputype == Loongson_3A) {
83 loongson_sysconf.cores_per_node = 4; 87 loongson_sysconf.cores_per_node = 4;
84 loongson_sysconf.cores_per_package = 4; 88 loongson_sysconf.cores_per_package = 4;
89 smp_group[0] = 0x900000003ff01000;
90 smp_group[1] = 0x900010003ff01000;
91 smp_group[2] = 0x900020003ff01000;
92 smp_group[3] = 0x900030003ff01000;
85 loongson_chipcfg[0] = 0x900000001fe00180; 93 loongson_chipcfg[0] = 0x900000001fe00180;
86 loongson_chipcfg[1] = 0x900010001fe00180; 94 loongson_chipcfg[1] = 0x900010001fe00180;
87 loongson_chipcfg[2] = 0x900020001fe00180; 95 loongson_chipcfg[2] = 0x900020001fe00180;
88 loongson_chipcfg[3] = 0x900030001fe00180; 96 loongson_chipcfg[3] = 0x900030001fe00180;
97 loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
98 } else if (ecpu->cputype == Loongson_3B) {
99 loongson_sysconf.cores_per_node = 4; /* One chip has 2 nodes */
100 loongson_sysconf.cores_per_package = 8;
101 smp_group[0] = 0x900000003ff01000;
102 smp_group[1] = 0x900010003ff05000;
103 smp_group[2] = 0x900020003ff09000;
104 smp_group[3] = 0x900030003ff0d000;
105 loongson_chipcfg[0] = 0x900000001fe00180;
106 loongson_chipcfg[1] = 0x900020001fe00180;
107 loongson_chipcfg[2] = 0x900040001fe00180;
108 loongson_chipcfg[3] = 0x900060001fe00180;
109 loongson_freqctrl[0] = 0x900000001fe001d0;
110 loongson_freqctrl[1] = 0x900020001fe001d0;
111 loongson_freqctrl[2] = 0x900040001fe001d0;
112 loongson_freqctrl[3] = 0x900060001fe001d0;
113 loongson_sysconf.ht_control_base = 0x90001EFDFB000000;
114 cpuhotplug_workaround = 1;
89 } else { 115 } else {
90 loongson_sysconf.cores_per_node = 1; 116 loongson_sysconf.cores_per_node = 1;
91 loongson_sysconf.cores_per_package = 1; 117 loongson_sysconf.cores_per_package = 1;
@@ -111,7 +137,6 @@ void __init prom_init_env(void)
111 loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown; 137 loongson_sysconf.poweroff_addr = boot_p->reset_system.Shutdown;
112 loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend; 138 loongson_sysconf.suspend_addr = boot_p->reset_system.DoSuspend;
113 139
114 loongson_sysconf.ht_control_base = 0x90000EFDFB000000;
115 loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios; 140 loongson_sysconf.vgabios_addr = boot_p->efi.smbios.vga_bios;
116 pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n", 141 pr_debug("Shutdown Addr: %llx, Restart Addr: %llx, VBIOS Addr: %llx\n",
117 loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr, 142 loongson_sysconf.poweroff_addr, loongson_sysconf.restart_addr,
@@ -129,6 +154,10 @@ void __init prom_init_env(void)
129 case PRID_REV_LOONGSON3A: 154 case PRID_REV_LOONGSON3A:
130 cpu_clock_freq = 900000000; 155 cpu_clock_freq = 900000000;
131 break; 156 break;
157 case PRID_REV_LOONGSON3B_R1:
158 case PRID_REV_LOONGSON3B_R2:
159 cpu_clock_freq = 1000000000;
160 break;
132 default: 161 default:
133 cpu_clock_freq = 100000000; 162 cpu_clock_freq = 100000000;
134 break; 163 break;
diff --git a/arch/mips/loongson/loongson-3/irq.c b/arch/mips/loongson/loongson-3/irq.c
index f240828181ff..ca1c62af5188 100644
--- a/arch/mips/loongson/loongson-3/irq.c
+++ b/arch/mips/loongson/loongson-3/irq.c
@@ -7,6 +7,8 @@
7#include <asm/i8259.h> 7#include <asm/i8259.h>
8#include <asm/mipsregs.h> 8#include <asm/mipsregs.h>
9 9
10#include "smp.h"
11
10unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15}; 12unsigned int ht_irq[] = {1, 3, 4, 5, 6, 7, 8, 12, 14, 15};
11 13
12static void ht_irqdispatch(void) 14static void ht_irqdispatch(void)
@@ -53,9 +55,15 @@ static inline void mask_loongson_irq(struct irq_data *d)
53 /* Workaround: UART IRQ may deliver to any core */ 55 /* Workaround: UART IRQ may deliver to any core */
54 if (d->irq == LOONGSON_UART_IRQ) { 56 if (d->irq == LOONGSON_UART_IRQ) {
55 int cpu = smp_processor_id(); 57 int cpu = smp_processor_id();
56 58 int node_id = cpu / loongson_sysconf.cores_per_node;
57 LOONGSON_INT_ROUTER_INTENCLR = 1 << 10; 59 int core_id = cpu % loongson_sysconf.cores_per_node;
58 LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu); 60 u64 intenclr_addr = smp_group[node_id] |
61 (u64)(&LOONGSON_INT_ROUTER_INTENCLR);
62 u64 introuter_lpc_addr = smp_group[node_id] |
63 (u64)(&LOONGSON_INT_ROUTER_LPC);
64
65 *(volatile u32 *)intenclr_addr = 1 << 10;
66 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
59 } 67 }
60} 68}
61 69
@@ -64,9 +72,15 @@ static inline void unmask_loongson_irq(struct irq_data *d)
64 /* Workaround: UART IRQ may deliver to any core */ 72 /* Workaround: UART IRQ may deliver to any core */
65 if (d->irq == LOONGSON_UART_IRQ) { 73 if (d->irq == LOONGSON_UART_IRQ) {
66 int cpu = smp_processor_id(); 74 int cpu = smp_processor_id();
67 75 int node_id = cpu / loongson_sysconf.cores_per_node;
68 LOONGSON_INT_ROUTER_INTENSET = 1 << 10; 76 int core_id = cpu % loongson_sysconf.cores_per_node;
69 LOONGSON_INT_ROUTER_LPC = 0x10 + (1<<cpu); 77 u64 intenset_addr = smp_group[node_id] |
78 (u64)(&LOONGSON_INT_ROUTER_INTENSET);
79 u64 introuter_lpc_addr = smp_group[node_id] |
80 (u64)(&LOONGSON_INT_ROUTER_LPC);
81
82 *(volatile u32 *)intenset_addr = 1 << 10;
83 *(volatile u8 *)introuter_lpc_addr = 0x10 + (1<<core_id);
70 } 84 }
71 85
72 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 86 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
diff --git a/arch/mips/loongson/loongson-3/smp.c b/arch/mips/loongson/loongson-3/smp.c
index ed0e2d0f87ab..74e827b4ec8f 100644
--- a/arch/mips/loongson/loongson-3/smp.c
+++ b/arch/mips/loongson/loongson-3/smp.c
@@ -31,6 +31,12 @@
31DEFINE_PER_CPU(int, cpu_state); 31DEFINE_PER_CPU(int, cpu_state);
32DEFINE_PER_CPU(uint32_t, core0_c0count); 32DEFINE_PER_CPU(uint32_t, core0_c0count);
33 33
34static void *ipi_set0_regs[16];
35static void *ipi_clear0_regs[16];
36static void *ipi_status0_regs[16];
37static void *ipi_en0_regs[16];
38static void *ipi_mailbox_buf[16];
39
34/* read a 32bit value from ipi register */ 40/* read a 32bit value from ipi register */
35#define loongson3_ipi_read32(addr) readl(addr) 41#define loongson3_ipi_read32(addr) readl(addr)
36/* read a 64bit value from ipi register */ 42/* read a 64bit value from ipi register */
@@ -48,100 +54,185 @@ DEFINE_PER_CPU(uint32_t, core0_c0count);
48 __wbflush(); \ 54 __wbflush(); \
49 } while (0) 55 } while (0)
50 56
51static void *ipi_set0_regs[] = { 57static void ipi_set0_regs_init(void)
52 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0), 58{
53 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0), 59 ipi_set0_regs[0] = (void *)
54 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0), 60 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + SET0);
55 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0), 61 ipi_set0_regs[1] = (void *)
56 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0), 62 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + SET0);
57 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0), 63 ipi_set0_regs[2] = (void *)
58 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0), 64 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + SET0);
59 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0), 65 ipi_set0_regs[3] = (void *)
60 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0), 66 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + SET0);
61 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0), 67 ipi_set0_regs[4] = (void *)
62 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0), 68 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + SET0);
63 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0), 69 ipi_set0_regs[5] = (void *)
64 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0), 70 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + SET0);
65 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0), 71 ipi_set0_regs[6] = (void *)
66 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0), 72 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + SET0);
67 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0), 73 ipi_set0_regs[7] = (void *)
68}; 74 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + SET0);
75 ipi_set0_regs[8] = (void *)
76 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + SET0);
77 ipi_set0_regs[9] = (void *)
78 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + SET0);
79 ipi_set0_regs[10] = (void *)
80 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + SET0);
81 ipi_set0_regs[11] = (void *)
82 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + SET0);
83 ipi_set0_regs[12] = (void *)
84 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + SET0);
85 ipi_set0_regs[13] = (void *)
86 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + SET0);
87 ipi_set0_regs[14] = (void *)
88 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + SET0);
89 ipi_set0_regs[15] = (void *)
90 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + SET0);
91}
69 92
70static void *ipi_clear0_regs[] = { 93static void ipi_clear0_regs_init(void)
71 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0), 94{
72 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0), 95 ipi_clear0_regs[0] = (void *)
73 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0), 96 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + CLEAR0);
74 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0), 97 ipi_clear0_regs[1] = (void *)
75 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0), 98 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + CLEAR0);
76 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0), 99 ipi_clear0_regs[2] = (void *)
77 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0), 100 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + CLEAR0);
78 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0), 101 ipi_clear0_regs[3] = (void *)
79 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0), 102 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + CLEAR0);
80 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0), 103 ipi_clear0_regs[4] = (void *)
81 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0), 104 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + CLEAR0);
82 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0), 105 ipi_clear0_regs[5] = (void *)
83 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0), 106 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + CLEAR0);
84 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0), 107 ipi_clear0_regs[6] = (void *)
85 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0), 108 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + CLEAR0);
86 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0), 109 ipi_clear0_regs[7] = (void *)
87}; 110 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + CLEAR0);
111 ipi_clear0_regs[8] = (void *)
112 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + CLEAR0);
113 ipi_clear0_regs[9] = (void *)
114 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + CLEAR0);
115 ipi_clear0_regs[10] = (void *)
116 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + CLEAR0);
117 ipi_clear0_regs[11] = (void *)
118 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + CLEAR0);
119 ipi_clear0_regs[12] = (void *)
120 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + CLEAR0);
121 ipi_clear0_regs[13] = (void *)
122 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + CLEAR0);
123 ipi_clear0_regs[14] = (void *)
124 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + CLEAR0);
125 ipi_clear0_regs[15] = (void *)
126 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + CLEAR0);
127}
88 128
89static void *ipi_status0_regs[] = { 129static void ipi_status0_regs_init(void)
90 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0), 130{
91 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0), 131 ipi_status0_regs[0] = (void *)
92 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0), 132 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + STATUS0);
93 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0), 133 ipi_status0_regs[1] = (void *)
94 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0), 134 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + STATUS0);
95 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0), 135 ipi_status0_regs[2] = (void *)
96 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0), 136 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + STATUS0);
97 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0), 137 ipi_status0_regs[3] = (void *)
98 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0), 138 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + STATUS0);
99 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0), 139 ipi_status0_regs[4] = (void *)
100 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0), 140 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + STATUS0);
101 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0), 141 ipi_status0_regs[5] = (void *)
102 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0), 142 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + STATUS0);
103 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0), 143 ipi_status0_regs[6] = (void *)
104 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0), 144 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + STATUS0);
105 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0), 145 ipi_status0_regs[7] = (void *)
106}; 146 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + STATUS0);
147 ipi_status0_regs[8] = (void *)
148 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + STATUS0);
149 ipi_status0_regs[9] = (void *)
150 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + STATUS0);
151 ipi_status0_regs[10] = (void *)
152 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + STATUS0);
153 ipi_status0_regs[11] = (void *)
154 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + STATUS0);
155 ipi_status0_regs[12] = (void *)
156 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + STATUS0);
157 ipi_status0_regs[13] = (void *)
158 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + STATUS0);
159 ipi_status0_regs[14] = (void *)
160 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + STATUS0);
161 ipi_status0_regs[15] = (void *)
162 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + STATUS0);
163}
107 164
108static void *ipi_en0_regs[] = { 165static void ipi_en0_regs_init(void)
109 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0), 166{
110 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0), 167 ipi_en0_regs[0] = (void *)
111 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0), 168 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + EN0);
112 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0), 169 ipi_en0_regs[1] = (void *)
113 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0), 170 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + EN0);
114 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0), 171 ipi_en0_regs[2] = (void *)
115 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0), 172 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + EN0);
116 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0), 173 ipi_en0_regs[3] = (void *)
117 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0), 174 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + EN0);
118 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0), 175 ipi_en0_regs[4] = (void *)
119 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0), 176 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + EN0);
120 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0), 177 ipi_en0_regs[5] = (void *)
121 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0), 178 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + EN0);
122 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0), 179 ipi_en0_regs[6] = (void *)
123 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0), 180 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + EN0);
124 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0), 181 ipi_en0_regs[7] = (void *)
125}; 182 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + EN0);
183 ipi_en0_regs[8] = (void *)
184 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + EN0);
185 ipi_en0_regs[9] = (void *)
186 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + EN0);
187 ipi_en0_regs[10] = (void *)
188 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + EN0);
189 ipi_en0_regs[11] = (void *)
190 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + EN0);
191 ipi_en0_regs[12] = (void *)
192 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + EN0);
193 ipi_en0_regs[13] = (void *)
194 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + EN0);
195 ipi_en0_regs[14] = (void *)
196 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + EN0);
197 ipi_en0_regs[15] = (void *)
198 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + EN0);
199}
126 200
127static void *ipi_mailbox_buf[] = { 201static void ipi_mailbox_buf_init(void)
128 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF), 202{
129 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF), 203 ipi_mailbox_buf[0] = (void *)
130 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF), 204 (SMP_CORE_GROUP0_BASE + SMP_CORE0_OFFSET + BUF);
131 (void *)(SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF), 205 ipi_mailbox_buf[1] = (void *)
132 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF), 206 (SMP_CORE_GROUP0_BASE + SMP_CORE1_OFFSET + BUF);
133 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF), 207 ipi_mailbox_buf[2] = (void *)
134 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF), 208 (SMP_CORE_GROUP0_BASE + SMP_CORE2_OFFSET + BUF);
135 (void *)(SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF), 209 ipi_mailbox_buf[3] = (void *)
136 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF), 210 (SMP_CORE_GROUP0_BASE + SMP_CORE3_OFFSET + BUF);
137 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF), 211 ipi_mailbox_buf[4] = (void *)
138 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF), 212 (SMP_CORE_GROUP1_BASE + SMP_CORE0_OFFSET + BUF);
139 (void *)(SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF), 213 ipi_mailbox_buf[5] = (void *)
140 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF), 214 (SMP_CORE_GROUP1_BASE + SMP_CORE1_OFFSET + BUF);
141 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF), 215 ipi_mailbox_buf[6] = (void *)
142 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF), 216 (SMP_CORE_GROUP1_BASE + SMP_CORE2_OFFSET + BUF);
143 (void *)(SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF), 217 ipi_mailbox_buf[7] = (void *)
144}; 218 (SMP_CORE_GROUP1_BASE + SMP_CORE3_OFFSET + BUF);
219 ipi_mailbox_buf[8] = (void *)
220 (SMP_CORE_GROUP2_BASE + SMP_CORE0_OFFSET + BUF);
221 ipi_mailbox_buf[9] = (void *)
222 (SMP_CORE_GROUP2_BASE + SMP_CORE1_OFFSET + BUF);
223 ipi_mailbox_buf[10] = (void *)
224 (SMP_CORE_GROUP2_BASE + SMP_CORE2_OFFSET + BUF);
225 ipi_mailbox_buf[11] = (void *)
226 (SMP_CORE_GROUP2_BASE + SMP_CORE3_OFFSET + BUF);
227 ipi_mailbox_buf[12] = (void *)
228 (SMP_CORE_GROUP3_BASE + SMP_CORE0_OFFSET + BUF);
229 ipi_mailbox_buf[13] = (void *)
230 (SMP_CORE_GROUP3_BASE + SMP_CORE1_OFFSET + BUF);
231 ipi_mailbox_buf[14] = (void *)
232 (SMP_CORE_GROUP3_BASE + SMP_CORE2_OFFSET + BUF);
233 ipi_mailbox_buf[15] = (void *)
234 (SMP_CORE_GROUP3_BASE + SMP_CORE3_OFFSET + BUF);
235}
145 236
146/* 237/*
147 * Simple enough, just poke the appropriate ipi register 238 * Simple enough, just poke the appropriate ipi register
@@ -248,6 +339,11 @@ static void __init loongson3_smp_setup(void)
248 __cpu_number_map[i] = ++num; 339 __cpu_number_map[i] = ++num;
249 __cpu_logical_map[num] = i; 340 __cpu_logical_map[num] = i;
250 } 341 }
342 ipi_set0_regs_init();
343 ipi_clear0_regs_init();
344 ipi_status0_regs_init();
345 ipi_en0_regs_init();
346 ipi_mailbox_buf_init();
251 pr_info("Detected %i available secondary CPU(s)\n", num); 347 pr_info("Detected %i available secondary CPU(s)\n", num);
252} 348}
253 349
@@ -315,7 +411,7 @@ static void loongson3_cpu_die(unsigned int cpu)
315 * flush all L1 entries at first. Then, another core (usually Core 0) can 411 * flush all L1 entries at first. Then, another core (usually Core 0) can
316 * safely disable the clock of the target core. loongson3_play_dead() is 412 * safely disable the clock of the target core. loongson3_play_dead() is
317 * called via CKSEG1 (uncached and unmmaped) */ 413 * called via CKSEG1 (uncached and unmmaped) */
318static void loongson3_play_dead(int *state_addr) 414static void loongson3a_play_dead(int *state_addr)
319{ 415{
320 register int val; 416 register int val;
321 register long cpuid, core, node, count; 417 register long cpuid, core, node, count;
@@ -377,6 +473,70 @@ static void loongson3_play_dead(int *state_addr)
377 : "a1"); 473 : "a1");
378} 474}
379 475
476static void loongson3b_play_dead(int *state_addr)
477{
478 register int val;
479 register long cpuid, core, node, count;
480 register void *addr, *base, *initfunc;
481
482 __asm__ __volatile__(
483 " .set push \n"
484 " .set noreorder \n"
485 " li %[addr], 0x80000000 \n" /* KSEG0 */
486 "1: cache 0, 0(%[addr]) \n" /* flush L1 ICache */
487 " cache 0, 1(%[addr]) \n"
488 " cache 0, 2(%[addr]) \n"
489 " cache 0, 3(%[addr]) \n"
490 " cache 1, 0(%[addr]) \n" /* flush L1 DCache */
491 " cache 1, 1(%[addr]) \n"
492 " cache 1, 2(%[addr]) \n"
493 " cache 1, 3(%[addr]) \n"
494 " addiu %[sets], %[sets], -1 \n"
495 " bnez %[sets], 1b \n"
496 " addiu %[addr], %[addr], 0x20 \n"
497 " li %[val], 0x7 \n" /* *state_addr = CPU_DEAD; */
498 " sw %[val], (%[state_addr]) \n"
499 " sync \n"
500 " cache 21, (%[state_addr]) \n" /* flush entry of *state_addr */
501 " .set pop \n"
502 : [addr] "=&r" (addr), [val] "=&r" (val)
503 : [state_addr] "r" (state_addr),
504 [sets] "r" (cpu_data[smp_processor_id()].dcache.sets));
505
506 __asm__ __volatile__(
507 " .set push \n"
508 " .set noreorder \n"
509 " .set mips64 \n"
510 " mfc0 %[cpuid], $15, 1 \n"
511 " andi %[cpuid], 0x3ff \n"
512 " dli %[base], 0x900000003ff01000 \n"
513 " andi %[core], %[cpuid], 0x3 \n"
514 " sll %[core], 8 \n" /* get core id */
515 " or %[base], %[base], %[core] \n"
516 " andi %[node], %[cpuid], 0xc \n"
517 " dsll %[node], 42 \n" /* get node id */
518 " or %[base], %[base], %[node] \n"
519 " dsrl %[node], 30 \n" /* 15:14 */
520 " or %[base], %[base], %[node] \n"
521 "1: li %[count], 0x100 \n" /* wait for init loop */
522 "2: bnez %[count], 2b \n" /* limit mailbox access */
523 " addiu %[count], -1 \n"
524 " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
525 " beqz %[initfunc], 1b \n"
526 " nop \n"
527 " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
528 " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
529 " ld $a1, 0x38(%[base]) \n"
530 " jr %[initfunc] \n" /* jump to initial PC */
531 " nop \n"
532 " .set pop \n"
533 : [core] "=&r" (core), [node] "=&r" (node),
534 [base] "=&r" (base), [cpuid] "=&r" (cpuid),
535 [count] "=&r" (count), [initfunc] "=&r" (initfunc)
536 : /* No Input */
537 : "a1");
538}
539
380void play_dead(void) 540void play_dead(void)
381{ 541{
382 int *state_addr; 542 int *state_addr;
@@ -384,31 +544,64 @@ void play_dead(void)
384 void (*play_dead_at_ckseg1)(int *); 544 void (*play_dead_at_ckseg1)(int *);
385 545
386 idle_task_exit(); 546 idle_task_exit();
387 play_dead_at_ckseg1 = 547 switch (loongson_sysconf.cputype) {
388 (void *)CKSEG1ADDR((unsigned long)loongson3_play_dead); 548 case Loongson_3A:
549 default:
550 play_dead_at_ckseg1 =
551 (void *)CKSEG1ADDR((unsigned long)loongson3a_play_dead);
552 break;
553 case Loongson_3B:
554 play_dead_at_ckseg1 =
555 (void *)CKSEG1ADDR((unsigned long)loongson3b_play_dead);
556 break;
557 }
389 state_addr = &per_cpu(cpu_state, cpu); 558 state_addr = &per_cpu(cpu_state, cpu);
390 mb(); 559 mb();
391 play_dead_at_ckseg1(state_addr); 560 play_dead_at_ckseg1(state_addr);
392} 561}
393 562
563void loongson3_disable_clock(int cpu)
564{
565 uint64_t core_id = cpu_data[cpu].core;
566 uint64_t package_id = cpu_data[cpu].package;
567
568 if (loongson_sysconf.cputype == Loongson_3A) {
569 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
570 } else if (loongson_sysconf.cputype == Loongson_3B) {
571 if (!cpuhotplug_workaround)
572 LOONGSON_FREQCTRL(package_id) &= ~(1 << (core_id * 4 + 3));
573 }
574}
575
576void loongson3_enable_clock(int cpu)
577{
578 uint64_t core_id = cpu_data[cpu].core;
579 uint64_t package_id = cpu_data[cpu].package;
580
581 if (loongson_sysconf.cputype == Loongson_3A) {
582 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
583 } else if (loongson_sysconf.cputype == Loongson_3B) {
584 if (!cpuhotplug_workaround)
585 LOONGSON_FREQCTRL(package_id) |= 1 << (core_id * 4 + 3);
586 }
587}
588
394#define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD | CPU_TASKS_FROZEN) 589#define CPU_POST_DEAD_FROZEN (CPU_POST_DEAD | CPU_TASKS_FROZEN)
395static int loongson3_cpu_callback(struct notifier_block *nfb, 590static int loongson3_cpu_callback(struct notifier_block *nfb,
396 unsigned long action, void *hcpu) 591 unsigned long action, void *hcpu)
397{ 592{
398 unsigned int cpu = (unsigned long)hcpu; 593 unsigned int cpu = (unsigned long)hcpu;
399 uint64_t core_id = cpu_data[cpu].core;
400 uint64_t package_id = cpu_data[cpu].package;
401 594
402 switch (action) { 595 switch (action) {
403 case CPU_POST_DEAD: 596 case CPU_POST_DEAD:
404 case CPU_POST_DEAD_FROZEN: 597 case CPU_POST_DEAD_FROZEN:
405 pr_info("Disable clock for CPU#%d\n", cpu); 598 pr_info("Disable clock for CPU#%d\n", cpu);
406 LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id)); 599 loongson3_disable_clock(cpu);
407 break; 600 break;
408 case CPU_UP_PREPARE: 601 case CPU_UP_PREPARE:
409 case CPU_UP_PREPARE_FROZEN: 602 case CPU_UP_PREPARE_FROZEN:
410 pr_info("Enable clock for CPU#%d\n", cpu); 603 pr_info("Enable clock for CPU#%d\n", cpu);
411 LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id); 604 loongson3_enable_clock(cpu);
412 break; 605 break;
413 } 606 }
414 607
diff --git a/arch/mips/loongson/loongson-3/smp.h b/arch/mips/loongson/loongson-3/smp.h
index 3453e8c4f2f0..d98ff654b7d7 100644
--- a/arch/mips/loongson/loongson-3/smp.h
+++ b/arch/mips/loongson/loongson-3/smp.h
@@ -1,29 +1,30 @@
1#ifndef __LOONGSON_SMP_H_ 1#ifndef __LOONGSON_SMP_H_
2#define __LOONGSON_SMP_H_ 2#define __LOONGSON_SMP_H_
3 3
4/* for Loongson-3A smp support */ 4/* for Loongson-3 smp support */
5extern unsigned long long smp_group[4];
5 6
6/* 4 groups(nodes) in maximum in numa case */ 7/* 4 groups(nodes) in maximum in numa case */
7#define SMP_CORE_GROUP0_BASE 0x900000003ff01000 8#define SMP_CORE_GROUP0_BASE (smp_group[0])
8#define SMP_CORE_GROUP1_BASE 0x900010003ff01000 9#define SMP_CORE_GROUP1_BASE (smp_group[1])
9#define SMP_CORE_GROUP2_BASE 0x900020003ff01000 10#define SMP_CORE_GROUP2_BASE (smp_group[2])
10#define SMP_CORE_GROUP3_BASE 0x900030003ff01000 11#define SMP_CORE_GROUP3_BASE (smp_group[3])
11 12
12/* 4 cores in each group(node) */ 13/* 4 cores in each group(node) */
13#define SMP_CORE0_OFFSET 0x000 14#define SMP_CORE0_OFFSET 0x000
14#define SMP_CORE1_OFFSET 0x100 15#define SMP_CORE1_OFFSET 0x100
15#define SMP_CORE2_OFFSET 0x200 16#define SMP_CORE2_OFFSET 0x200
16#define SMP_CORE3_OFFSET 0x300 17#define SMP_CORE3_OFFSET 0x300
17 18
18/* ipi registers offsets */ 19/* ipi registers offsets */
19#define STATUS0 0x00 20#define STATUS0 0x00
20#define EN0 0x04 21#define EN0 0x04
21#define SET0 0x08 22#define SET0 0x08
22#define CLEAR0 0x0c 23#define CLEAR0 0x0c
23#define STATUS1 0x10 24#define STATUS1 0x10
24#define MASK1 0x14 25#define MASK1 0x14
25#define SET1 0x18 26#define SET1 0x18
26#define CLEAR1 0x1c 27#define CLEAR1 0x1c
27#define BUF 0x20 28#define BUF 0x20
28 29
29#endif 30#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-19 07:16:18 -0500