diff options
author | Markos Chandras <markos.chandras@imgtec.com> | 2014-01-03 04:21:20 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 18:09:14 -0400 |
commit | 8483b14aaa81e9567dd69977f22efc4c8536184f (patch) | |
tree | d8203306a9895b5f200bfa8018c954a4e7e829ac /arch/mips/lib | |
parent | cd26cb41ece49ce0dd0f43d88f4d3386ca42a825 (diff) |
MIPS: lib: memset: Whitespace fixes
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/lib')
-rw-r--r-- | arch/mips/lib/memset.S | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S index 0580194e7402..d8579857a81d 100644 --- a/arch/mips/lib/memset.S +++ b/arch/mips/lib/memset.S | |||
@@ -74,7 +74,7 @@ | |||
74 | .align 5 | 74 | .align 5 |
75 | LEAF(memset) | 75 | LEAF(memset) |
76 | beqz a1, 1f | 76 | beqz a1, 1f |
77 | move v0, a0 /* result */ | 77 | move v0, a0 /* result */ |
78 | 78 | ||
79 | andi a1, 0xff /* spread fillword */ | 79 | andi a1, 0xff /* spread fillword */ |
80 | LONG_SLL t1, a1, 8 | 80 | LONG_SLL t1, a1, 8 |
@@ -90,7 +90,7 @@ LEAF(memset) | |||
90 | FEXPORT(__bzero) | 90 | FEXPORT(__bzero) |
91 | sltiu t0, a2, STORSIZE /* very small region? */ | 91 | sltiu t0, a2, STORSIZE /* very small region? */ |
92 | bnez t0, .Lsmall_memset | 92 | bnez t0, .Lsmall_memset |
93 | andi t0, a0, STORMASK /* aligned? */ | 93 | andi t0, a0, STORMASK /* aligned? */ |
94 | 94 | ||
95 | #ifdef CONFIG_CPU_MICROMIPS | 95 | #ifdef CONFIG_CPU_MICROMIPS |
96 | move t8, a1 /* used by 'swp' instruction */ | 96 | move t8, a1 /* used by 'swp' instruction */ |
@@ -98,12 +98,12 @@ FEXPORT(__bzero) | |||
98 | #endif | 98 | #endif |
99 | #ifndef CONFIG_CPU_DADDI_WORKAROUNDS | 99 | #ifndef CONFIG_CPU_DADDI_WORKAROUNDS |
100 | beqz t0, 1f | 100 | beqz t0, 1f |
101 | PTR_SUBU t0, STORSIZE /* alignment in bytes */ | 101 | PTR_SUBU t0, STORSIZE /* alignment in bytes */ |
102 | #else | 102 | #else |
103 | .set noat | 103 | .set noat |
104 | li AT, STORSIZE | 104 | li AT, STORSIZE |
105 | beqz t0, 1f | 105 | beqz t0, 1f |
106 | PTR_SUBU t0, AT /* alignment in bytes */ | 106 | PTR_SUBU t0, AT /* alignment in bytes */ |
107 | .set at | 107 | .set at |
108 | #endif | 108 | #endif |
109 | 109 | ||
@@ -120,7 +120,7 @@ FEXPORT(__bzero) | |||
120 | 1: ori t1, a2, 0x3f /* # of full blocks */ | 120 | 1: ori t1, a2, 0x3f /* # of full blocks */ |
121 | xori t1, 0x3f | 121 | xori t1, 0x3f |
122 | beqz t1, .Lmemset_partial /* no block to fill */ | 122 | beqz t1, .Lmemset_partial /* no block to fill */ |
123 | andi t0, a2, 0x40-STORSIZE | 123 | andi t0, a2, 0x40-STORSIZE |
124 | 124 | ||
125 | PTR_ADDU t1, a0 /* end address */ | 125 | PTR_ADDU t1, a0 /* end address */ |
126 | .set reorder | 126 | .set reorder |
@@ -145,7 +145,7 @@ FEXPORT(__bzero) | |||
145 | .set at | 145 | .set at |
146 | #endif | 146 | #endif |
147 | jr t1 | 147 | jr t1 |
148 | PTR_ADDU a0, t0 /* dest ptr */ | 148 | PTR_ADDU a0, t0 /* dest ptr */ |
149 | 149 | ||
150 | .set push | 150 | .set push |
151 | .set noreorder | 151 | .set noreorder |
@@ -155,7 +155,7 @@ FEXPORT(__bzero) | |||
155 | andi a2, STORMASK /* At most one long to go */ | 155 | andi a2, STORMASK /* At most one long to go */ |
156 | 156 | ||
157 | beqz a2, 1f | 157 | beqz a2, 1f |
158 | PTR_ADDU a0, a2 /* What's left */ | 158 | PTR_ADDU a0, a2 /* What's left */ |
159 | R10KCBARRIER(0(ra)) | 159 | R10KCBARRIER(0(ra)) |
160 | #ifdef __MIPSEB__ | 160 | #ifdef __MIPSEB__ |
161 | EX(LONG_S_R, a1, -1(a0), .Llast_fixup) | 161 | EX(LONG_S_R, a1, -1(a0), .Llast_fixup) |
@@ -164,24 +164,24 @@ FEXPORT(__bzero) | |||
164 | EX(LONG_S_L, a1, -1(a0), .Llast_fixup) | 164 | EX(LONG_S_L, a1, -1(a0), .Llast_fixup) |
165 | #endif | 165 | #endif |
166 | 1: jr ra | 166 | 1: jr ra |
167 | move a2, zero | 167 | move a2, zero |
168 | 168 | ||
169 | .Lsmall_memset: | 169 | .Lsmall_memset: |
170 | beqz a2, 2f | 170 | beqz a2, 2f |
171 | PTR_ADDU t1, a0, a2 | 171 | PTR_ADDU t1, a0, a2 |
172 | 172 | ||
173 | 1: PTR_ADDIU a0, 1 /* fill bytewise */ | 173 | 1: PTR_ADDIU a0, 1 /* fill bytewise */ |
174 | R10KCBARRIER(0(ra)) | 174 | R10KCBARRIER(0(ra)) |
175 | bne t1, a0, 1b | 175 | bne t1, a0, 1b |
176 | sb a1, -1(a0) | 176 | sb a1, -1(a0) |
177 | 177 | ||
178 | 2: jr ra /* done */ | 178 | 2: jr ra /* done */ |
179 | move a2, zero | 179 | move a2, zero |
180 | END(memset) | 180 | END(memset) |
181 | 181 | ||
182 | .Lfirst_fixup: | 182 | .Lfirst_fixup: |
183 | jr ra | 183 | jr ra |
184 | nop | 184 | nop |
185 | 185 | ||
186 | .Lfwd_fixup: | 186 | .Lfwd_fixup: |
187 | PTR_L t0, TI_TASK($28) | 187 | PTR_L t0, TI_TASK($28) |
@@ -189,7 +189,7 @@ FEXPORT(__bzero) | |||
189 | LONG_L t0, THREAD_BUADDR(t0) | 189 | LONG_L t0, THREAD_BUADDR(t0) |
190 | LONG_ADDU a2, t1 | 190 | LONG_ADDU a2, t1 |
191 | jr ra | 191 | jr ra |
192 | LONG_SUBU a2, t0 | 192 | LONG_SUBU a2, t0 |
193 | 193 | ||
194 | .Lpartial_fixup: | 194 | .Lpartial_fixup: |
195 | PTR_L t0, TI_TASK($28) | 195 | PTR_L t0, TI_TASK($28) |
@@ -197,8 +197,8 @@ FEXPORT(__bzero) | |||
197 | LONG_L t0, THREAD_BUADDR(t0) | 197 | LONG_L t0, THREAD_BUADDR(t0) |
198 | LONG_ADDU a2, t1 | 198 | LONG_ADDU a2, t1 |
199 | jr ra | 199 | jr ra |
200 | LONG_SUBU a2, t0 | 200 | LONG_SUBU a2, t0 |
201 | 201 | ||
202 | .Llast_fixup: | 202 | .Llast_fixup: |
203 | jr ra | 203 | jr ra |
204 | andi v1, a2, STORMASK | 204 | andi v1, a2, STORMASK |