Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS updates from Ralf Baechle:

 o Add basic support for the Mediatek/Ralink Wireless SoC family.

 o The Qualcomm Atheros platform is extended by support for the new
   QCA955X SoC series as well as a bunch of patches that get the code
   ready for OF support.

 o Lantiq and BCM47XX platform have a few improvements and bug fixes.

 o MIPS has sent a few patches that get the kernel ready for the
   upcoming microMIPS support.

 o The rest of the series is made up of small bug fixes and cleanups
   that relate to various parts of the MIPS code.  The biggy in there is
   a whitespace cleanup.  After I was sent another set of whitespace
   cleanup patches I decided it was the time to clean the whitespace
   "issues" for once and and that touches many files below arch/mips/.

Fix up silly conflicts, mostly due to whitespace cleanups.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (105 commits)
  MIPS: Quit exporting kernel internel break codes to uapi/asm/break.h
  MIPS: remove broken conditional inside vpe loader code
  MIPS: SMTC: fix implicit declaration of set_vi_handler
  MIPS: early_printk: drop __init annotations
  MIPS: Probe for and report hardware virtualization support.
  MIPS: ath79: add support for the Qualcomm Atheros AP136-010 board
  MIPS: ath79: add USB controller registration code for the QCA955X SoCs
  MIPS: ath79: add PCI controller registration code for the QCA955X SoCs
  MIPS: ath79: add WMAC registration code for the QCA955X SoCs
  MIPS: ath79: register UART for the QCA955X SoCs
  MIPS: ath79: add QCA955X specific glue to ath79_device_reset_{set, clear}
  MIPS: ath79: add GPIO setup code for the QCA955X SoCs
  MIPS: ath79: add IRQ handling code for the QCA955X SoCs
  MIPS: ath79: add clock setup code for the QCA955X SoCs
  MIPS: ath79: add SoC detection code for the QCA955X SoCs
  MIPS: ath79: add early printk support for the QCA955X SoCs
  MIPS: ath79: fix WMAC IRQ resource assignment
  mips: reserve elfcorehdr
  mips: Make sure kernel memory is in iomem
  MIPS: ath79: use dynamically allocated USB platform devices
  ...

1 files changed, 17 insertions, 17 deletions

diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 65192c06781e..c5c40dad0bbf 100644
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -156,15 +156,15 @@
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR
-#define LDREST  LOADL
+#define LDREST  LOADL
 #define STFIRST STORER
-#define STREST  STOREL
+#define STREST  STOREL
 #define SHIFT_DISCARD SLLV
 #else
 #define LDFIRST LOADL
-#define LDREST  LOADR
+#define LDREST  LOADR
 #define STFIRST STOREL
-#define STREST  STORER
+#define STREST  STORER
 #define SHIFT_DISCARD SRLV
 #endif
 
@@ -235,7 +235,7 @@ __copy_user_common:
          * src and dst are aligned; need to compute rem
          */
 .Lboth_aligned:
-         SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
+         SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
         beqz    t0, .Lcleanup_both_aligned # len < 8*NBYTES
          and    rem, len, (8*NBYTES-1)   # rem = len % (8*NBYTES)
         PREF(   0, 3*32(src) )
@@ -313,7 +313,7 @@ EXC(	STORE	t0, 0(dst),		.Ls_exc_p1u)
         /*
          * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
          * A loop would do only a byte at a time with possible branch
-         * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE
+         * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE
          * because can't assume read-access to dst.  Instead, use
          * STREST dst, which doesn't require read access to dst.
          *
@@ -327,7 +327,7 @@ EXC(	STORE	t0, 0(dst),		.Ls_exc_p1u)
         li      bits, 8*NBYTES
         SLL     rem, len, 3     # rem = number of bits to keep
 EXC(    LOAD    t0, 0(src),             .Ll_exc)
-        SUB     bits, bits, rem # bits = number of bits to discard
+        SUB     bits, bits, rem # bits = number of bits to discard
         SHIFT_DISCARD t0, t0, bits
 EXC(    STREST  t0, -1(t1),             .Ls_exc)
         jr      ra
@@ -343,7 +343,7 @@ EXC(	STREST	t0, -1(t1),		.Ls_exc)
          * Set match = (src and dst have same alignment)
          */
 #define match rem
-EXC(    LDFIRST t3, FIRST(0)(src),      .Ll_exc)
+EXC(    LDFIRST t3, FIRST(0)(src),      .Ll_exc)
         ADD     t2, zero, NBYTES
 EXC(    LDREST  t3, REST(0)(src),       .Ll_exc_copy)
         SUB     t2, t2, t1      # t2 = number of bytes copied
@@ -357,10 +357,10 @@ EXC(	STFIRST t3, FIRST(0)(dst),	.Ls_exc)
          ADD    src, src, t2
 
 .Lsrc_unaligned_dst_aligned:
-        SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
+        SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
         PREF(   0, 3*32(src) )
         beqz    t0, .Lcleanup_src_unaligned
-         and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
+         and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
         PREF(   1, 3*32(dst) )
 1:
 /*
@@ -370,13 +370,13 @@ EXC(	STFIRST t3, FIRST(0)(dst),	.Ls_exc)
  * are to the same unit (unless src is aligned, but it's not).
  */
         R10KCBARRIER(0(ra))
-EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
-EXC(    LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
-        SUB     len, len, 4*NBYTES
+EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+EXC(    LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
+        SUB     len, len, 4*NBYTES
 EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
 EXC(    LDREST  t1, REST(1)(src),       .Ll_exc_copy)
-EXC(    LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
-EXC(    LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
+EXC(    LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
+EXC(    LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
 EXC(    LDREST  t2, REST(2)(src),       .Ll_exc_copy)
 EXC(    LDREST  t3, REST(3)(src),       .Ll_exc_copy)
         PREF(   0, 9*32(src) )          # 0 is PREF_LOAD  (not streamed)
@@ -388,7 +388,7 @@ EXC(	STORE	t0, UNIT(0)(dst),	.Ls_exc_p4u)
 EXC(    STORE   t1, UNIT(1)(dst),       .Ls_exc_p3u)
 EXC(    STORE   t2, UNIT(2)(dst),       .Ls_exc_p2u)
 EXC(    STORE   t3, UNIT(3)(dst),       .Ls_exc_p1u)
-        PREF(   1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)
+        PREF(   1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)
         .set    reorder                         /* DADDI_WAR */
         ADD     dst, dst, 4*NBYTES
         bne     len, rem, 1b
@@ -502,7 +502,7 @@ EXC(	lb	t1, 0(src),	.Ll_exc)
 
 
 #define SEXC(n)                                                 \
-        .set    reorder;                        /* DADDI_WAR */ \
+        .set    reorder;                        /* DADDI_WAR */ \
 .Ls_exc_p ## n ## u:                                            \
         ADD     len, len, n*NBYTES;                             \
         jr      ra;                                             \