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authorLinus Torvalds <torvalds@linux-foundation.org>2012-05-29 21:27:19 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-05-29 21:27:19 -0400
commit7e5b2db77b05746613516599c916a8cc2e321077 (patch)
treec3ec333ff7b77bcc8e456a3a3d19bf20f5c651b8 /arch/mips/lantiq
parent227d1e4319ffd8729781941d92f4ae4d85beecd9 (diff)
parentc819baf31f5f91fbb06b2c93de2d5b8c8d096f3f (diff)
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "The whole series has been sitting in -next for quite a while with no complaints. The last change to the series was before the weekend the removal of an SPI patch which Grant - even though previously acked by himself - appeared to raise objections. So I removed it until the situation is clarified. Other than that all the patches have the acks from their respective maintainers, all MIPS and x86 defconfigs are building fine and I'm not aware of any problems introduced by this series. Among the key features for this patch series is a sizable patchset for Lantiq which among other things introduces support for Lantiq's flagship product, the FALCON SOC. It also means that the opensource developers behind this patchset have overtaken Lantiq's competing inhouse development team that was working behind closed doors. Less noteworthy the ath79 patchset which adds support for a few more chip variants, cleanups and fixes. Finally the usual dose of tweaking of generic code." Fix up trivial conflicts in arch/mips/lantiq/xway/gpio_{ebu,stp}.c where printk spelling fixes clashed with file move and eventual removal of the printk. * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (81 commits) MIPS: lantiq: remove orphaned code MIPS: Remove all -Wall and almost all -Werror usage from arch/mips. MIPS: lantiq: implement support for FALCON soc MTD: MIPS: lantiq: verify that the NOR interface is available on falcon soc MTD: MIPS: lantiq: implement OF support watchdog: MIPS: lantiq: implement OF support and minor fixes SERIAL: MIPS: lantiq: implement OF support GPIO: MIPS: lantiq: convert gpio-stp-xway to OF GPIO: MIPS: lantiq: convert gpio-mm-lantiq to OF and of_mm_gpio GPIO: MIPS: lantiq: move gpio-stp and gpio-ebu to the subsystem folder MIPS: pci: convert lantiq driver to OF MIPS: lantiq: convert dma to platform driver MIPS: lantiq: implement support for clkdev api MIPS: lantiq: drop ltq_gpio_request() and gpio_to_irq() OF: MIPS: lantiq: implement irq_domain support OF: MIPS: lantiq: implement OF support MIPS: lantiq: drop mips_machine support OF: PCI: const usage needed by MIPS MIPS: Cavium: Remove smp_reserve_lock. MIPS: Move cache setup to setup_arch(). ...
Diffstat (limited to 'arch/mips/lantiq')
-rw-r--r--arch/mips/lantiq/Kconfig16
-rw-r--r--arch/mips/lantiq/Makefile5
-rw-r--r--arch/mips/lantiq/Platform1
-rw-r--r--arch/mips/lantiq/clk.c146
-rw-r--r--arch/mips/lantiq/clk.h68
-rw-r--r--arch/mips/lantiq/devices.c120
-rw-r--r--arch/mips/lantiq/devices.h23
-rw-r--r--arch/mips/lantiq/dts/Makefile4
-rw-r--r--arch/mips/lantiq/dts/danube.dtsi105
-rw-r--r--arch/mips/lantiq/dts/easy50712.dts113
-rw-r--r--arch/mips/lantiq/early_printk.c17
-rw-r--r--arch/mips/lantiq/falcon/Makefile1
-rw-r--r--arch/mips/lantiq/falcon/prom.c87
-rw-r--r--arch/mips/lantiq/falcon/reset.c90
-rw-r--r--arch/mips/lantiq/falcon/sysctrl.c260
-rw-r--r--arch/mips/lantiq/irq.c255
-rw-r--r--arch/mips/lantiq/machtypes.h20
-rw-r--r--arch/mips/lantiq/prom.c74
-rw-r--r--arch/mips/lantiq/prom.h8
-rw-r--r--arch/mips/lantiq/setup.c66
-rw-r--r--arch/mips/lantiq/xway/Kconfig23
-rw-r--r--arch/mips/lantiq/xway/Makefile8
-rw-r--r--arch/mips/lantiq/xway/clk-ase.c48
-rw-r--r--arch/mips/lantiq/xway/clk-xway.c223
-rw-r--r--arch/mips/lantiq/xway/clk.c151
-rw-r--r--arch/mips/lantiq/xway/devices.c119
-rw-r--r--arch/mips/lantiq/xway/devices.h20
-rw-r--r--arch/mips/lantiq/xway/dma.c61
-rw-r--r--arch/mips/lantiq/xway/ebu.c52
-rw-r--r--arch/mips/lantiq/xway/gpio.c12
-rw-r--r--arch/mips/lantiq/xway/gpio_ebu.c126
-rw-r--r--arch/mips/lantiq/xway/gpio_stp.c157
-rw-r--r--arch/mips/lantiq/xway/mach-easy50601.c57
-rw-r--r--arch/mips/lantiq/xway/mach-easy50712.c74
-rw-r--r--arch/mips/lantiq/xway/pmu.c69
-rw-r--r--arch/mips/lantiq/xway/prom-ase.c39
-rw-r--r--arch/mips/lantiq/xway/prom-xway.c54
-rw-r--r--arch/mips/lantiq/xway/prom.c115
-rw-r--r--arch/mips/lantiq/xway/reset.c77
-rw-r--r--arch/mips/lantiq/xway/setup-ase.c19
-rw-r--r--arch/mips/lantiq/xway/setup-xway.c20
-rw-r--r--arch/mips/lantiq/xway/sysctrl.c371
42 files changed, 1791 insertions, 1583 deletions
diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
index 3fccf2104513..20bdf40b3efa 100644
--- a/arch/mips/lantiq/Kconfig
+++ b/arch/mips/lantiq/Kconfig
@@ -16,8 +16,22 @@ config SOC_XWAY
16 bool "XWAY" 16 bool "XWAY"
17 select SOC_TYPE_XWAY 17 select SOC_TYPE_XWAY
18 select HW_HAS_PCI 18 select HW_HAS_PCI
19
20config SOC_FALCON
21 bool "FALCON"
22
23endchoice
24
25choice
26 prompt "Devicetree"
27
28config DT_EASY50712
29 bool "Easy50712"
30 depends on SOC_XWAY
19endchoice 31endchoice
20 32
21source "arch/mips/lantiq/xway/Kconfig" 33config PCI_LANTIQ
34 bool "PCI Support"
35 depends on SOC_XWAY && PCI
22 36
23endif 37endif
diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile
index e5dae0e24b00..d6bdc579419f 100644
--- a/arch/mips/lantiq/Makefile
+++ b/arch/mips/lantiq/Makefile
@@ -4,8 +4,11 @@
4# under the terms of the GNU General Public License version 2 as published 4# under the terms of the GNU General Public License version 2 as published
5# by the Free Software Foundation. 5# by the Free Software Foundation.
6 6
7obj-y := irq.o setup.o clk.o prom.o devices.o 7obj-y := irq.o clk.o prom.o
8
9obj-y += dts/
8 10
9obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
10 12
11obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ 13obj-$(CONFIG_SOC_TYPE_XWAY) += xway/
14obj-$(CONFIG_SOC_FALCON) += falcon/
diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform
index f3dff05722de..b3ec49838fd7 100644
--- a/arch/mips/lantiq/Platform
+++ b/arch/mips/lantiq/Platform
@@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/
6cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq 6cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq
7load-$(CONFIG_LANTIQ) = 0xffffffff80002000 7load-$(CONFIG_LANTIQ) = 0xffffffff80002000
8cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway 8cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
9cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index 412814fdd3ee..d3bcc33f4699 100644
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -12,6 +12,7 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/types.h> 13#include <linux/types.h>
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <linux/clkdev.h>
15#include <linux/err.h> 16#include <linux/err.h>
16#include <linux/list.h> 17#include <linux/list.h>
17 18
@@ -22,44 +23,32 @@
22#include <lantiq_soc.h> 23#include <lantiq_soc.h>
23 24
24#include "clk.h" 25#include "clk.h"
26#include "prom.h"
25 27
26struct clk { 28/* lantiq socs have 3 static clocks */
27 const char *name; 29static struct clk cpu_clk_generic[3];
28 unsigned long rate;
29 unsigned long (*get_rate) (void);
30};
31 30
32static struct clk *cpu_clk; 31void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io)
33static int cpu_clk_cnt; 32{
33 cpu_clk_generic[0].rate = cpu;
34 cpu_clk_generic[1].rate = fpi;
35 cpu_clk_generic[2].rate = io;
36}
34 37
35/* lantiq socs have 3 static clocks */ 38struct clk *clk_get_cpu(void)
36static struct clk cpu_clk_generic[] = { 39{
37 { 40 return &cpu_clk_generic[0];
38 .name = "cpu", 41}
39 .get_rate = ltq_get_cpu_hz, 42
40 }, { 43struct clk *clk_get_fpi(void)
41 .name = "fpi", 44{
42 .get_rate = ltq_get_fpi_hz, 45 return &cpu_clk_generic[1];
43 }, { 46}
44 .name = "io", 47EXPORT_SYMBOL_GPL(clk_get_fpi);
45 .get_rate = ltq_get_io_region_clock, 48
46 }, 49struct clk *clk_get_io(void)
47};
48
49static struct resource ltq_cgu_resource = {
50 .name = "cgu",
51 .start = LTQ_CGU_BASE_ADDR,
52 .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1,
53 .flags = IORESOURCE_MEM,
54};
55
56/* remapped clock register range */
57void __iomem *ltq_cgu_membase;
58
59void clk_init(void)
60{ 50{
61 cpu_clk = cpu_clk_generic; 51 return &cpu_clk_generic[2];
62 cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
63} 52}
64 53
65static inline int clk_good(struct clk *clk) 54static inline int clk_good(struct clk *clk)
@@ -82,38 +71,71 @@ unsigned long clk_get_rate(struct clk *clk)
82} 71}
83EXPORT_SYMBOL(clk_get_rate); 72EXPORT_SYMBOL(clk_get_rate);
84 73
85struct clk *clk_get(struct device *dev, const char *id) 74int clk_set_rate(struct clk *clk, unsigned long rate)
86{ 75{
87 int i; 76 if (unlikely(!clk_good(clk)))
88 77 return 0;
89 for (i = 0; i < cpu_clk_cnt; i++) 78 if (clk->rates && *clk->rates) {
90 if (!strcmp(id, cpu_clk[i].name)) 79 unsigned long *r = clk->rates;
91 return &cpu_clk[i]; 80
92 BUG(); 81 while (*r && (*r != rate))
93 return ERR_PTR(-ENOENT); 82 r++;
94} 83 if (!*r) {
95EXPORT_SYMBOL(clk_get); 84 pr_err("clk %s.%s: trying to set invalid rate %ld\n",
96 85 clk->cl.dev_id, clk->cl.con_id, rate);
97void clk_put(struct clk *clk) 86 return -1;
98{ 87 }
99 /* not used */ 88 }
89 clk->rate = rate;
90 return 0;
100} 91}
101EXPORT_SYMBOL(clk_put); 92EXPORT_SYMBOL(clk_set_rate);
102 93
103int clk_enable(struct clk *clk) 94int clk_enable(struct clk *clk)
104{ 95{
105 /* not used */ 96 if (unlikely(!clk_good(clk)))
106 return 0; 97 return -1;
98
99 if (clk->enable)
100 return clk->enable(clk);
101
102 return -1;
107} 103}
108EXPORT_SYMBOL(clk_enable); 104EXPORT_SYMBOL(clk_enable);
109 105
110void clk_disable(struct clk *clk) 106void clk_disable(struct clk *clk)
111{ 107{
112 /* not used */ 108 if (unlikely(!clk_good(clk)))
109 return;
110
111 if (clk->disable)
112 clk->disable(clk);
113} 113}
114EXPORT_SYMBOL(clk_disable); 114EXPORT_SYMBOL(clk_disable);
115 115
116static inline u32 ltq_get_counter_resolution(void) 116int clk_activate(struct clk *clk)
117{
118 if (unlikely(!clk_good(clk)))
119 return -1;
120
121 if (clk->activate)
122 return clk->activate(clk);
123
124 return -1;
125}
126EXPORT_SYMBOL(clk_activate);
127
128void clk_deactivate(struct clk *clk)
129{
130 if (unlikely(!clk_good(clk)))
131 return;
132
133 if (clk->deactivate)
134 clk->deactivate(clk);
135}
136EXPORT_SYMBOL(clk_deactivate);
137
138static inline u32 get_counter_resolution(void)
117{ 139{
118 u32 res; 140 u32 res;
119 141
@@ -133,21 +155,11 @@ void __init plat_time_init(void)
133{ 155{
134 struct clk *clk; 156 struct clk *clk;
135 157
136 if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0) 158 ltq_soc_init();
137 panic("Failed to insert cgu memory");
138 159
139 if (request_mem_region(ltq_cgu_resource.start, 160 clk = clk_get_cpu();
140 resource_size(&ltq_cgu_resource), "cgu") < 0) 161 mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution();
141 panic("Failed to request cgu memory");
142
143 ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start,
144 resource_size(&ltq_cgu_resource));
145 if (!ltq_cgu_membase) {
146 pr_err("Failed to remap cgu memory\n");
147 unreachable();
148 }
149 clk = clk_get(0, "cpu");
150 mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
151 write_c0_compare(read_c0_count()); 162 write_c0_compare(read_c0_count());
163 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
152 clk_put(clk); 164 clk_put(clk);
153} 165}
diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h
index 3328925f2c3f..fa670602b91b 100644
--- a/arch/mips/lantiq/clk.h
+++ b/arch/mips/lantiq/clk.h
@@ -9,10 +9,70 @@
9#ifndef _LTQ_CLK_H__ 9#ifndef _LTQ_CLK_H__
10#define _LTQ_CLK_H__ 10#define _LTQ_CLK_H__
11 11
12extern void clk_init(void); 12#include <linux/clkdev.h>
13 13
14extern unsigned long ltq_get_cpu_hz(void); 14/* clock speeds */
15extern unsigned long ltq_get_fpi_hz(void); 15#define CLOCK_33M 33333333
16extern unsigned long ltq_get_io_region_clock(void); 16#define CLOCK_60M 60000000
17#define CLOCK_62_5M 62500000
18#define CLOCK_83M 83333333
19#define CLOCK_83_5M 83500000
20#define CLOCK_98_304M 98304000
21#define CLOCK_100M 100000000
22#define CLOCK_111M 111111111
23#define CLOCK_125M 125000000
24#define CLOCK_133M 133333333
25#define CLOCK_150M 150000000
26#define CLOCK_166M 166666666
27#define CLOCK_167M 166666667
28#define CLOCK_196_608M 196608000
29#define CLOCK_200M 200000000
30#define CLOCK_250M 250000000
31#define CLOCK_266M 266666666
32#define CLOCK_300M 300000000
33#define CLOCK_333M 333333333
34#define CLOCK_393M 393215332
35#define CLOCK_400M 400000000
36#define CLOCK_500M 500000000
37#define CLOCK_600M 600000000
38
39/* clock out speeds */
40#define CLOCK_32_768K 32768
41#define CLOCK_1_536M 1536000
42#define CLOCK_2_5M 2500000
43#define CLOCK_12M 12000000
44#define CLOCK_24M 24000000
45#define CLOCK_25M 25000000
46#define CLOCK_30M 30000000
47#define CLOCK_40M 40000000
48#define CLOCK_48M 48000000
49#define CLOCK_50M 50000000
50#define CLOCK_60M 60000000
51
52struct clk {
53 struct clk_lookup cl;
54 unsigned long rate;
55 unsigned long *rates;
56 unsigned int module;
57 unsigned int bits;
58 unsigned long (*get_rate) (void);
59 int (*enable) (struct clk *clk);
60 void (*disable) (struct clk *clk);
61 int (*activate) (struct clk *clk);
62 void (*deactivate) (struct clk *clk);
63 void (*reboot) (struct clk *clk);
64};
65
66extern void clkdev_add_static(unsigned long cpu, unsigned long fpi,
67 unsigned long io);
68
69extern unsigned long ltq_danube_cpu_hz(void);
70extern unsigned long ltq_danube_fpi_hz(void);
71
72extern unsigned long ltq_ar9_cpu_hz(void);
73extern unsigned long ltq_ar9_fpi_hz(void);
74
75extern unsigned long ltq_vr9_cpu_hz(void);
76extern unsigned long ltq_vr9_fpi_hz(void);
17 77
18#endif 78#endif
diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c
deleted file mode 100644
index de1cb2bcd79a..000000000000
--- a/arch/mips/lantiq/devices.c
+++ /dev/null
@@ -1,120 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/export.h>
11#include <linux/types.h>
12#include <linux/string.h>
13#include <linux/kernel.h>
14#include <linux/reboot.h>
15#include <linux/platform_device.h>
16#include <linux/leds.h>
17#include <linux/etherdevice.h>
18#include <linux/time.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21
22#include <asm/bootinfo.h>
23#include <asm/irq.h>
24
25#include <lantiq_soc.h>
26
27#include "devices.h"
28
29/* nor flash */
30static struct resource ltq_nor_resource = {
31 .name = "nor",
32 .start = LTQ_FLASH_START,
33 .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
34 .flags = IORESOURCE_MEM,
35};
36
37static struct platform_device ltq_nor = {
38 .name = "ltq_nor",
39 .resource = &ltq_nor_resource,
40 .num_resources = 1,
41};
42
43void __init ltq_register_nor(struct physmap_flash_data *data)
44{
45 ltq_nor.dev.platform_data = data;
46 platform_device_register(&ltq_nor);
47}
48
49/* watchdog */
50static struct resource ltq_wdt_resource = {
51 .name = "watchdog",
52 .start = LTQ_WDT_BASE_ADDR,
53 .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
54 .flags = IORESOURCE_MEM,
55};
56
57void __init ltq_register_wdt(void)
58{
59 platform_device_register_simple("ltq_wdt", 0, &ltq_wdt_resource, 1);
60}
61
62/* asc ports */
63static struct resource ltq_asc0_resources[] = {
64 {
65 .name = "asc0",
66 .start = LTQ_ASC0_BASE_ADDR,
67 .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
68 .flags = IORESOURCE_MEM,
69 },
70 IRQ_RES(tx, LTQ_ASC_TIR(0)),
71 IRQ_RES(rx, LTQ_ASC_RIR(0)),
72 IRQ_RES(err, LTQ_ASC_EIR(0)),
73};
74
75static struct resource ltq_asc1_resources[] = {
76 {
77 .name = "asc1",
78 .start = LTQ_ASC1_BASE_ADDR,
79 .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
80 .flags = IORESOURCE_MEM,
81 },
82 IRQ_RES(tx, LTQ_ASC_TIR(1)),
83 IRQ_RES(rx, LTQ_ASC_RIR(1)),
84 IRQ_RES(err, LTQ_ASC_EIR(1)),
85};
86
87void __init ltq_register_asc(int port)
88{
89 switch (port) {
90 case 0:
91 platform_device_register_simple("ltq_asc", 0,
92 ltq_asc0_resources, ARRAY_SIZE(ltq_asc0_resources));
93 break;
94 case 1:
95 platform_device_register_simple("ltq_asc", 1,
96 ltq_asc1_resources, ARRAY_SIZE(ltq_asc1_resources));
97 break;
98 default:
99 break;
100 }
101}
102
103#ifdef CONFIG_PCI
104/* pci */
105static struct platform_device ltq_pci = {
106 .name = "ltq_pci",
107 .num_resources = 0,
108};
109
110void __init ltq_register_pci(struct ltq_pci_data *data)
111{
112 ltq_pci.dev.platform_data = data;
113 platform_device_register(&ltq_pci);
114}
115#else
116void __init ltq_register_pci(struct ltq_pci_data *data)
117{
118 pr_err("kernel is compiled without PCI support\n");
119}
120#endif
diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h
deleted file mode 100644
index 2947bb19a528..000000000000
--- a/arch/mips/lantiq/devices.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_DEVICES_H__
10#define _LTQ_DEVICES_H__
11
12#include <lantiq_platform.h>
13#include <linux/mtd/physmap.h>
14
15#define IRQ_RES(resname, irq) \
16 {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
17
18extern void ltq_register_nor(struct physmap_flash_data *data);
19extern void ltq_register_wdt(void);
20extern void ltq_register_asc(int port);
21extern void ltq_register_pci(struct ltq_pci_data *data);
22
23#endif
diff --git a/arch/mips/lantiq/dts/Makefile b/arch/mips/lantiq/dts/Makefile
new file mode 100644
index 000000000000..674fca45f72d
--- /dev/null
+++ b/arch/mips/lantiq/dts/Makefile
@@ -0,0 +1,4 @@
1obj-$(CONFIG_DT_EASY50712) := easy50712.dtb.o
2
3$(obj)/%.dtb: $(obj)/%.dts
4 $(call if_changed,dtc)
diff --git a/arch/mips/lantiq/dts/danube.dtsi b/arch/mips/lantiq/dts/danube.dtsi
new file mode 100644
index 000000000000..3a4520f009cf
--- /dev/null
+++ b/arch/mips/lantiq/dts/danube.dtsi
@@ -0,0 +1,105 @@
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "lantiq,xway", "lantiq,danube";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips24Kc";
9 };
10 };
11
12 biu@1F800000 {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "lantiq,biu", "simple-bus";
16 reg = <0x1F800000 0x800000>;
17 ranges = <0x0 0x1F800000 0x7FFFFF>;
18
19 icu0: icu@80200 {
20 #interrupt-cells = <1>;
21 interrupt-controller;
22 compatible = "lantiq,icu";
23 reg = <0x80200 0x120>;
24 };
25
26 watchdog@803F0 {
27 compatible = "lantiq,wdt";
28 reg = <0x803F0 0x10>;
29 };
30 };
31
32 sram@1F000000 {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "lantiq,sram";
36 reg = <0x1F000000 0x800000>;
37 ranges = <0x0 0x1F000000 0x7FFFFF>;
38
39 eiu0: eiu@101000 {
40 #interrupt-cells = <1>;
41 interrupt-controller;
42 interrupt-parent;
43 compatible = "lantiq,eiu-xway";
44 reg = <0x101000 0x1000>;
45 };
46
47 pmu0: pmu@102000 {
48 compatible = "lantiq,pmu-xway";
49 reg = <0x102000 0x1000>;
50 };
51
52 cgu0: cgu@103000 {
53 compatible = "lantiq,cgu-xway";
54 reg = <0x103000 0x1000>;
55 #clock-cells = <1>;
56 };
57
58 rcu0: rcu@203000 {
59 compatible = "lantiq,rcu-xway";
60 reg = <0x203000 0x1000>;
61 };
62 };
63
64 fpi@10000000 {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "lantiq,fpi", "simple-bus";
68 ranges = <0x0 0x10000000 0xEEFFFFF>;
69 reg = <0x10000000 0xEF00000>;
70
71 gptu@E100A00 {
72 compatible = "lantiq,gptu-xway";
73 reg = <0xE100A00 0x100>;
74 };
75
76 serial@E100C00 {
77 compatible = "lantiq,asc";
78 reg = <0xE100C00 0x400>;
79 interrupt-parent = <&icu0>;
80 interrupts = <112 113 114>;
81 };
82
83 dma0: dma@E104100 {
84 compatible = "lantiq,dma-xway";
85 reg = <0xE104100 0x800>;
86 };
87
88 ebu0: ebu@E105300 {
89 compatible = "lantiq,ebu-xway";
90 reg = <0xE105300 0x100>;
91 };
92
93 pci0: pci@E105400 {
94 #address-cells = <3>;
95 #size-cells = <2>;
96 #interrupt-cells = <1>;
97 compatible = "lantiq,pci-xway";
98 bus-range = <0x0 0x0>;
99 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
100 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
101 reg = <0x7000000 0x8000 /* config space */
102 0xE105400 0x400>; /* pci bridge */
103 };
104 };
105};
diff --git a/arch/mips/lantiq/dts/easy50712.dts b/arch/mips/lantiq/dts/easy50712.dts
new file mode 100644
index 000000000000..68c17310bc82
--- /dev/null
+++ b/arch/mips/lantiq/dts/easy50712.dts
@@ -0,0 +1,113 @@
1/dts-v1/;
2
3/include/ "danube.dtsi"
4
5/ {
6 chosen {
7 bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
8 };
9
10 memory@0 {
11 reg = <0x0 0x2000000>;
12 };
13
14 fpi@10000000 {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 localbus@0 {
18 #address-cells = <2>;
19 #size-cells = <1>;
20 ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
21 1 0 0x4000000 0x4000010>; /* addsel1 */
22 compatible = "lantiq,localbus", "simple-bus";
23
24 nor-boot@0 {
25 compatible = "lantiq,nor";
26 bank-width = <2>;
27 reg = <0 0x0 0x2000000>;
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 partition@0 {
32 label = "uboot";
33 reg = <0x00000 0x10000>; /* 64 KB */
34 };
35
36 partition@10000 {
37 label = "uboot_env";
38 reg = <0x10000 0x10000>; /* 64 KB */
39 };
40
41 partition@20000 {
42 label = "linux";
43 reg = <0x20000 0x3d0000>;
44 };
45
46 partition@400000 {
47 label = "rootfs";
48 reg = <0x400000 0x400000>;
49 };
50 };
51 };
52
53 gpio: pinmux@E100B10 {
54 compatible = "lantiq,pinctrl-xway";
55 pinctrl-names = "default";
56 pinctrl-0 = <&state_default>;
57
58 #gpio-cells = <2>;
59 gpio-controller;
60 reg = <0xE100B10 0xA0>;
61
62 state_default: pinmux {
63 stp {
64 lantiq,groups = "stp";
65 lantiq,function = "stp";
66 };
67 exin {
68 lantiq,groups = "exin1";
69 lantiq,function = "exin";
70 };
71 pci {
72 lantiq,groups = "gnt1";
73 lantiq,function = "pci";
74 };
75 conf_out {
76 lantiq,pins = "io4", "io5", "io6"; /* stp */
77 lantiq,open-drain;
78 lantiq,pull = <0>;
79 };
80 };
81 };
82
83 etop@E180000 {
84 compatible = "lantiq,etop-xway";
85 reg = <0xE180000 0x40000>;
86 interrupt-parent = <&icu0>;
87 interrupts = <73 78>;
88 phy-mode = "rmii";
89 mac-address = [ 00 11 22 33 44 55 ];
90 };
91
92 stp0: stp@E100BB0 {
93 #gpio-cells = <2>;
94 compatible = "lantiq,gpio-stp-xway";
95 gpio-controller;
96 reg = <0xE100BB0 0x40>;
97
98 lantiq,shadow = <0xfff>;
99 lantiq,groups = <0x3>;
100 };
101
102 pci@E105400 {
103 lantiq,bus-clock = <33333333>;
104 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
105 interrupt-map = <
106 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
107 >;
108 gpios-reset = <&gpio 21 0>;
109 req-mask = <0x1>; /* GNT1 */
110 };
111
112 };
113};
diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c
index 972e05f87631..9b28d0940ef4 100644
--- a/arch/mips/lantiq/early_printk.c
+++ b/arch/mips/lantiq/early_printk.c
@@ -6,17 +6,16 @@
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org> 6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */ 7 */
8 8
9#include <linux/init.h>
10#include <linux/cpu.h> 9#include <linux/cpu.h>
11
12#include <lantiq.h>
13#include <lantiq_soc.h> 10#include <lantiq_soc.h>
14 11
15/* no ioremap possible at this early stage, lets use KSEG1 instead */
16#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
17#define ASC_BUF 1024 12#define ASC_BUF 1024
18#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) 13#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048))
19#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) 14#ifdef __BIG_ENDIAN
15#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
16#else
17#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020))
18#endif
20#define TXMASK 0x3F00 19#define TXMASK 0x3F00
21#define TXOFFSET 8 20#define TXOFFSET 8
22 21
@@ -27,7 +26,7 @@ void prom_putchar(char c)
27 local_irq_save(flags); 26 local_irq_save(flags);
28 do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); 27 do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET);
29 if (c == '\n') 28 if (c == '\n')
30 ltq_w32('\r', LTQ_ASC_TBUF); 29 ltq_w8('\r', LTQ_ASC_TBUF);
31 ltq_w32(c, LTQ_ASC_TBUF); 30 ltq_w8(c, LTQ_ASC_TBUF);
32 local_irq_restore(flags); 31 local_irq_restore(flags);
33} 32}
diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile
new file mode 100644
index 000000000000..ff220f97693d
--- /dev/null
+++ b/arch/mips/lantiq/falcon/Makefile
@@ -0,0 +1 @@
obj-y := prom.o reset.o sysctrl.o
diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
new file mode 100644
index 000000000000..c1d278f05a3a
--- /dev/null
+++ b/arch/mips/lantiq/falcon/prom.c
@@ -0,0 +1,87 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
7 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/kernel.h>
11#include <asm/io.h>
12
13#include <lantiq_soc.h>
14
15#include "../prom.h"
16
17#define SOC_FALCON "Falcon"
18#define SOC_FALCON_D "Falcon-D"
19#define SOC_FALCON_V "Falcon-V"
20#define SOC_FALCON_M "Falcon-M"
21
22#define COMP_FALCON "lantiq,falcon"
23
24#define PART_SHIFT 12
25#define PART_MASK 0x0FFFF000
26#define REV_SHIFT 28
27#define REV_MASK 0xF0000000
28#define SREV_SHIFT 22
29#define SREV_MASK 0x03C00000
30#define TYPE_SHIFT 26
31#define TYPE_MASK 0x3C000000
32
33/* reset, nmi and ejtag exception vectors */
34#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
35#define BOOT_RVEC (BOOT_REG_BASE | 0x00)
36#define BOOT_NVEC (BOOT_REG_BASE | 0x04)
37#define BOOT_EVEC (BOOT_REG_BASE | 0x08)
38
39void __init ltq_soc_nmi_setup(void)
40{
41 extern void (*nmi_handler)(void);
42
43 ltq_w32((unsigned long)&nmi_handler, (void *)BOOT_NVEC);
44}
45
46void __init ltq_soc_ejtag_setup(void)
47{
48 extern void (*ejtag_debug_handler)(void);
49
50 ltq_w32((unsigned long)&ejtag_debug_handler, (void *)BOOT_EVEC);
51}
52
53void __init ltq_soc_detect(struct ltq_soc_info *i)
54{
55 u32 type;
56 i->partnum = (ltq_r32(FALCON_CHIPID) & PART_MASK) >> PART_SHIFT;
57 i->rev = (ltq_r32(FALCON_CHIPID) & REV_MASK) >> REV_SHIFT;
58 i->srev = ((ltq_r32(FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT);
59 i->compatible = COMP_FALCON;
60 i->type = SOC_TYPE_FALCON;
61 sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'),
62 i->rev & 0x7, (i->srev & 0x3) + 1);
63
64 switch (i->partnum) {
65 case SOC_ID_FALCON:
66 type = (ltq_r32(FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT;
67 switch (type) {
68 case 0:
69 i->name = SOC_FALCON_D;
70 break;
71 case 1:
72 i->name = SOC_FALCON_V;
73 break;
74 case 2:
75 i->name = SOC_FALCON_M;
76 break;
77 default:
78 i->name = SOC_FALCON;
79 break;
80 }
81 break;
82
83 default:
84 unreachable();
85 break;
86 }
87}
diff --git a/arch/mips/lantiq/falcon/reset.c b/arch/mips/lantiq/falcon/reset.c
new file mode 100644
index 000000000000..568248253426
--- /dev/null
+++ b/arch/mips/lantiq/falcon/reset.c
@@ -0,0 +1,90 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
7 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/pm.h>
13#include <asm/reboot.h>
14#include <linux/export.h>
15
16#include <lantiq_soc.h>
17
18/* CPU0 Reset Source Register */
19#define SYS1_CPU0RS 0x0040
20/* reset cause mask */
21#define CPU0RS_MASK 0x0003
22/* CPU0 Boot Mode Register */
23#define SYS1_BM 0x00a0
24/* boot mode mask */
25#define BM_MASK 0x0005
26
27/* allow platform code to find out what surce we booted from */
28unsigned char ltq_boot_select(void)
29{
30 return ltq_sys1_r32(SYS1_BM) & BM_MASK;
31}
32
33/* allow the watchdog driver to find out what the boot reason was */
34int ltq_reset_cause(void)
35{
36 return ltq_sys1_r32(SYS1_CPU0RS) & CPU0RS_MASK;
37}
38EXPORT_SYMBOL_GPL(ltq_reset_cause);
39
40#define BOOT_REG_BASE (KSEG1 | 0x1F200000)
41#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20)
42#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24)
43#define BOOT_PW1 0x4C545100
44#define BOOT_PW2 0x0051544C
45
46#define WDT_REG_BASE (KSEG1 | 0x1F8803F0)
47#define WDT_PW1 0x00BE0000
48#define WDT_PW2 0x00DC0000
49
50static void machine_restart(char *command)
51{
52 local_irq_disable();
53
54 /* reboot magic */
55 ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */
56 ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */
57 ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */
58
59 /* watchdog magic */
60 ltq_w32(WDT_PW1, (void *)WDT_REG_BASE);
61 ltq_w32(WDT_PW2 |
62 (0x3 << 26) | /* PWL */
63 (0x2 << 24) | /* CLKDIV */
64 (0x1 << 31) | /* enable */
65 (1), /* reload */
66 (void *)WDT_REG_BASE);
67 unreachable();
68}
69
70static void machine_halt(void)
71{
72 local_irq_disable();
73 unreachable();
74}
75
76static void machine_power_off(void)
77{
78 local_irq_disable();
79 unreachable();
80}
81
82static int __init mips_reboot_setup(void)
83{
84 _machine_restart = machine_restart;
85 _machine_halt = machine_halt;
86 pm_power_off = machine_power_off;
87 return 0;
88}
89
90arch_initcall(mips_reboot_setup);
diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
new file mode 100644
index 000000000000..ba0123d13d40
--- /dev/null
+++ b/arch/mips/lantiq/falcon/sysctrl.c
@@ -0,0 +1,260 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com>
7 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
8 */
9
10#include <linux/ioport.h>
11#include <linux/export.h>
12#include <linux/clkdev.h>
13#include <linux/of_address.h>
14#include <asm/delay.h>
15
16#include <lantiq_soc.h>
17
18#include "../clk.h"
19
20/* infrastructure control register */
21#define SYS1_INFRAC 0x00bc
22/* Configuration fuses for drivers and pll */
23#define STATUS_CONFIG 0x0040
24
25/* GPE frequency selection */
26#define GPPC_OFFSET 24
27#define GPEFREQ_MASK 0x00000C0
28#define GPEFREQ_OFFSET 10
29/* Clock status register */
30#define SYSCTL_CLKS 0x0000
31/* Clock enable register */
32#define SYSCTL_CLKEN 0x0004
33/* Clock clear register */
34#define SYSCTL_CLKCLR 0x0008
35/* Activation Status Register */
36#define SYSCTL_ACTS 0x0020
37/* Activation Register */
38#define SYSCTL_ACT 0x0024
39/* Deactivation Register */
40#define SYSCTL_DEACT 0x0028
41/* reboot Register */
42#define SYSCTL_RBT 0x002c
43/* CPU0 Clock Control Register */
44#define SYS1_CPU0CC 0x0040
45/* HRST_OUT_N Control Register */
46#define SYS1_HRSTOUTC 0x00c0
47/* clock divider bit */
48#define CPU0CC_CPUDIV 0x0001
49
50/* Activation Status Register */
51#define ACTS_ASC1_ACT 0x00000800
52#define ACTS_I2C_ACT 0x00004000
53#define ACTS_P0 0x00010000
54#define ACTS_P1 0x00010000
55#define ACTS_P2 0x00020000
56#define ACTS_P3 0x00020000
57#define ACTS_P4 0x00040000
58#define ACTS_PADCTRL0 0x00100000
59#define ACTS_PADCTRL1 0x00100000
60#define ACTS_PADCTRL2 0x00200000
61#define ACTS_PADCTRL3 0x00200000
62#define ACTS_PADCTRL4 0x00400000
63
64#define sysctl_w32(m, x, y) ltq_w32((x), sysctl_membase[m] + (y))
65#define sysctl_r32(m, x) ltq_r32(sysctl_membase[m] + (x))
66#define sysctl_w32_mask(m, clear, set, reg) \
67 sysctl_w32(m, (sysctl_r32(m, reg) & ~(clear)) | (set), reg)
68
69#define status_w32(x, y) ltq_w32((x), status_membase + (y))
70#define status_r32(x) ltq_r32(status_membase + (x))
71
72static void __iomem *sysctl_membase[3], *status_membase;
73void __iomem *ltq_sys1_membase, *ltq_ebu_membase;
74
75void falcon_trigger_hrst(int level)
76{
77 sysctl_w32(SYSCTL_SYS1, level & 1, SYS1_HRSTOUTC);
78}
79
80static inline void sysctl_wait(struct clk *clk,
81 unsigned int test, unsigned int reg)
82{
83 int err = 1000000;
84
85 do {} while (--err && ((sysctl_r32(clk->module, reg)
86 & clk->bits) != test));
87 if (!err)
88 pr_err("module de/activation failed %d %08X %08X %08X\n",
89 clk->module, clk->bits, test,
90 sysctl_r32(clk->module, reg) & clk->bits);
91}
92
93static int sysctl_activate(struct clk *clk)
94{
95 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
96 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT);
97 sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
98 return 0;
99}
100
101static void sysctl_deactivate(struct clk *clk)
102{
103 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
104 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT);
105 sysctl_wait(clk, 0, SYSCTL_ACTS);
106}
107
108static int sysctl_clken(struct clk *clk)
109{
110 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN);
111 sysctl_wait(clk, clk->bits, SYSCTL_CLKS);
112 return 0;
113}
114
115static void sysctl_clkdis(struct clk *clk)
116{
117 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR);
118 sysctl_wait(clk, 0, SYSCTL_CLKS);
119}
120
121static void sysctl_reboot(struct clk *clk)
122{
123 unsigned int act;
124 unsigned int bits;
125
126 act = sysctl_r32(clk->module, SYSCTL_ACT);
127 bits = ~act & clk->bits;
128 if (bits != 0) {
129 sysctl_w32(clk->module, bits, SYSCTL_CLKEN);
130 sysctl_w32(clk->module, bits, SYSCTL_ACT);
131 sysctl_wait(clk, bits, SYSCTL_ACTS);
132 }
133 sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT);
134 sysctl_wait(clk, clk->bits, SYSCTL_ACTS);
135}
136
137/* enable the ONU core */
138static void falcon_gpe_enable(void)
139{
140 unsigned int freq;
141 unsigned int status;
142
143 /* if if the clock is already enabled */
144 status = sysctl_r32(SYSCTL_SYS1, SYS1_INFRAC);
145 if (status & (1 << (GPPC_OFFSET + 1)))
146 return;
147
148 if (status_r32(STATUS_CONFIG) == 0)
149 freq = 1; /* use 625MHz on unfused chip */
150 else
151 freq = (status_r32(STATUS_CONFIG) &
152 GPEFREQ_MASK) >>
153 GPEFREQ_OFFSET;
154
155 /* apply new frequency */
156 sysctl_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1),
157 freq << (GPPC_OFFSET + 2) , SYS1_INFRAC);
158 udelay(1);
159
160 /* enable new frequency */
161 sysctl_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC);
162 udelay(1);
163}
164
165static inline void clkdev_add_sys(const char *dev, unsigned int module,
166 unsigned int bits)
167{
168 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
169
170 clk->cl.dev_id = dev;
171 clk->cl.con_id = NULL;
172 clk->cl.clk = clk;
173 clk->module = module;
174 clk->activate = sysctl_activate;
175 clk->deactivate = sysctl_deactivate;
176 clk->enable = sysctl_clken;
177 clk->disable = sysctl_clkdis;
178 clk->reboot = sysctl_reboot;
179 clkdev_add(&clk->cl);
180}
181
182void __init ltq_soc_init(void)
183{
184 struct device_node *np_status =
185 of_find_compatible_node(NULL, NULL, "lantiq,status-falcon");
186 struct device_node *np_ebu =
187 of_find_compatible_node(NULL, NULL, "lantiq,ebu-falcon");
188 struct device_node *np_sys1 =
189 of_find_compatible_node(NULL, NULL, "lantiq,sys1-falcon");
190 struct device_node *np_syseth =
191 of_find_compatible_node(NULL, NULL, "lantiq,syseth-falcon");
192 struct device_node *np_sysgpe =
193 of_find_compatible_node(NULL, NULL, "lantiq,sysgpe-falcon");
194 struct resource res_status, res_ebu, res_sys[3];
195 int i;
196
197 /* check if all the core register ranges are available */
198 if (!np_status || !np_ebu || !np_sys1 || !np_syseth || !np_sysgpe)
199 panic("Failed to load core nodes from devicetree");
200
201 if (of_address_to_resource(np_status, 0, &res_status) ||
202 of_address_to_resource(np_ebu, 0, &res_ebu) ||
203 of_address_to_resource(np_sys1, 0, &res_sys[0]) ||
204 of_address_to_resource(np_syseth, 0, &res_sys[1]) ||
205 of_address_to_resource(np_sysgpe, 0, &res_sys[2]))
206 panic("Failed to get core resources");
207
208 if ((request_mem_region(res_status.start, resource_size(&res_status),
209 res_status.name) < 0) ||
210 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
211 res_ebu.name) < 0) ||
212 (request_mem_region(res_sys[0].start,
213 resource_size(&res_sys[0]),
214 res_sys[0].name) < 0) ||
215 (request_mem_region(res_sys[1].start,
216 resource_size(&res_sys[1]),
217 res_sys[1].name) < 0) ||
218 (request_mem_region(res_sys[2].start,
219 resource_size(&res_sys[2]),
220 res_sys[2].name) < 0))
221 pr_err("Failed to request core reources");
222
223 status_membase = ioremap_nocache(res_status.start,
224 resource_size(&res_status));
225 ltq_ebu_membase = ioremap_nocache(res_ebu.start,
226 resource_size(&res_ebu));
227
228 if (!status_membase || !ltq_ebu_membase)
229 panic("Failed to remap core resources");
230
231 for (i = 0; i < 3; i++) {
232 sysctl_membase[i] = ioremap_nocache(res_sys[i].start,
233 resource_size(&res_sys[i]));
234 if (!sysctl_membase[i])
235 panic("Failed to remap sysctrl resources");
236 }
237 ltq_sys1_membase = sysctl_membase[0];
238
239 falcon_gpe_enable();
240
241 /* get our 3 static rates for cpu, fpi and io clocks */
242 if (ltq_sys1_r32(SYS1_CPU0CC) & CPU0CC_CPUDIV)
243 clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M);
244 else
245 clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M);
246
247 /* add our clock domains */
248 clkdev_add_sys("1d810000.gpio", SYSCTL_SYSETH, ACTS_P0);
249 clkdev_add_sys("1d810100.gpio", SYSCTL_SYSETH, ACTS_P2);
250 clkdev_add_sys("1e800100.gpio", SYSCTL_SYS1, ACTS_P1);
251 clkdev_add_sys("1e800200.gpio", SYSCTL_SYS1, ACTS_P3);
252 clkdev_add_sys("1e800300.gpio", SYSCTL_SYS1, ACTS_P4);
253 clkdev_add_sys("1db01000.pad", SYSCTL_SYSETH, ACTS_PADCTRL0);
254 clkdev_add_sys("1db02000.pad", SYSCTL_SYSETH, ACTS_PADCTRL2);
255 clkdev_add_sys("1e800400.pad", SYSCTL_SYS1, ACTS_PADCTRL1);
256 clkdev_add_sys("1e800500.pad", SYSCTL_SYS1, ACTS_PADCTRL3);
257 clkdev_add_sys("1e800600.pad", SYSCTL_SYS1, ACTS_PADCTRL4);
258 clkdev_add_sys("1e100C00.serial", SYSCTL_SYS1, ACTS_ASC1_ACT);
259 clkdev_add_sys("1e200000.i2c", SYSCTL_SYS1, ACTS_I2C_ACT);
260}
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index d673731c538a..57c1a4e51408 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -9,6 +9,11 @@
9 9
10#include <linux/interrupt.h> 10#include <linux/interrupt.h>
11#include <linux/ioport.h> 11#include <linux/ioport.h>
12#include <linux/sched.h>
13#include <linux/irqdomain.h>
14#include <linux/of_platform.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
12 17
13#include <asm/bootinfo.h> 18#include <asm/bootinfo.h>
14#include <asm/irq_cpu.h> 19#include <asm/irq_cpu.h>
@@ -16,7 +21,7 @@
16#include <lantiq_soc.h> 21#include <lantiq_soc.h>
17#include <irq.h> 22#include <irq.h>
18 23
19/* register definitions */ 24/* register definitions - internal irqs */
20#define LTQ_ICU_IM0_ISR 0x0000 25#define LTQ_ICU_IM0_ISR 0x0000
21#define LTQ_ICU_IM0_IER 0x0008 26#define LTQ_ICU_IM0_IER 0x0008
22#define LTQ_ICU_IM0_IOSR 0x0010 27#define LTQ_ICU_IM0_IOSR 0x0010
@@ -25,6 +30,7 @@
25#define LTQ_ICU_IM1_ISR 0x0028 30#define LTQ_ICU_IM1_ISR 0x0028
26#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR) 31#define LTQ_ICU_OFFSET (LTQ_ICU_IM1_ISR - LTQ_ICU_IM0_ISR)
27 32
33/* register definitions - external irqs */
28#define LTQ_EIU_EXIN_C 0x0000 34#define LTQ_EIU_EXIN_C 0x0000
29#define LTQ_EIU_EXIN_INIC 0x0004 35#define LTQ_EIU_EXIN_INIC 0x0004
30#define LTQ_EIU_EXIN_INEN 0x000C 36#define LTQ_EIU_EXIN_INEN 0x000C
@@ -37,10 +43,14 @@
37#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1) 43#define LTQ_EIU_IR4 (INT_NUM_IM1_IRL0 + 1)
38#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2) 44#define LTQ_EIU_IR5 (INT_NUM_IM1_IRL0 + 2)
39#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30) 45#define LTQ_EIU_IR6 (INT_NUM_IM2_IRL0 + 30)
40 46#define XWAY_EXIN_COUNT 3
41#define MAX_EIU 6 47#define MAX_EIU 6
42 48
43/* irqs generated by device attached to the EBU need to be acked in 49/* the performance counter */
50#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
51
52/*
53 * irqs generated by devices attached to the EBU need to be acked in
44 * a special manner 54 * a special manner
45 */ 55 */
46#define LTQ_ICU_EBU_IRQ 22 56#define LTQ_ICU_EBU_IRQ 22
@@ -51,6 +61,17 @@
51#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) 61#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
52#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) 62#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
53 63
64/* our 2 ipi interrupts for VSMP */
65#define MIPS_CPU_IPI_RESCHED_IRQ 0
66#define MIPS_CPU_IPI_CALL_IRQ 1
67
68/* we have a cascade of 8 irqs */
69#define MIPS_CPU_IRQ_CASCADE 8
70
71#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
72int gic_present;
73#endif
74
54static unsigned short ltq_eiu_irq[MAX_EIU] = { 75static unsigned short ltq_eiu_irq[MAX_EIU] = {
55 LTQ_EIU_IR0, 76 LTQ_EIU_IR0,
56 LTQ_EIU_IR1, 77 LTQ_EIU_IR1,
@@ -60,64 +81,51 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = {
60 LTQ_EIU_IR5, 81 LTQ_EIU_IR5,
61}; 82};
62 83
63static struct resource ltq_icu_resource = { 84static int exin_avail;
64 .name = "icu",
65 .start = LTQ_ICU_BASE_ADDR,
66 .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1,
67 .flags = IORESOURCE_MEM,
68};
69
70static struct resource ltq_eiu_resource = {
71 .name = "eiu",
72 .start = LTQ_EIU_BASE_ADDR,
73 .end = LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
74 .flags = IORESOURCE_MEM,
75};
76
77static void __iomem *ltq_icu_membase; 85static void __iomem *ltq_icu_membase;
78static void __iomem *ltq_eiu_membase; 86static void __iomem *ltq_eiu_membase;
79 87
80void ltq_disable_irq(struct irq_data *d) 88void ltq_disable_irq(struct irq_data *d)
81{ 89{
82 u32 ier = LTQ_ICU_IM0_IER; 90 u32 ier = LTQ_ICU_IM0_IER;
83 int irq_nr = d->irq - INT_NUM_IRQ0; 91 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
84 92
85 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); 93 ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
86 irq_nr %= INT_NUM_IM_OFFSET; 94 offset %= INT_NUM_IM_OFFSET;
87 ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); 95 ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
88} 96}
89 97
90void ltq_mask_and_ack_irq(struct irq_data *d) 98void ltq_mask_and_ack_irq(struct irq_data *d)
91{ 99{
92 u32 ier = LTQ_ICU_IM0_IER; 100 u32 ier = LTQ_ICU_IM0_IER;
93 u32 isr = LTQ_ICU_IM0_ISR; 101 u32 isr = LTQ_ICU_IM0_ISR;
94 int irq_nr = d->irq - INT_NUM_IRQ0; 102 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
95 103
96 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); 104 ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
97 isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); 105 isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
98 irq_nr %= INT_NUM_IM_OFFSET; 106 offset %= INT_NUM_IM_OFFSET;
99 ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); 107 ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
100 ltq_icu_w32((1 << irq_nr), isr); 108 ltq_icu_w32(BIT(offset), isr);
101} 109}
102 110
103static void ltq_ack_irq(struct irq_data *d) 111static void ltq_ack_irq(struct irq_data *d)
104{ 112{
105 u32 isr = LTQ_ICU_IM0_ISR; 113 u32 isr = LTQ_ICU_IM0_ISR;
106 int irq_nr = d->irq - INT_NUM_IRQ0; 114 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
107 115
108 isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); 116 isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
109 irq_nr %= INT_NUM_IM_OFFSET; 117 offset %= INT_NUM_IM_OFFSET;
110 ltq_icu_w32((1 << irq_nr), isr); 118 ltq_icu_w32(BIT(offset), isr);
111} 119}
112 120
113void ltq_enable_irq(struct irq_data *d) 121void ltq_enable_irq(struct irq_data *d)
114{ 122{
115 u32 ier = LTQ_ICU_IM0_IER; 123 u32 ier = LTQ_ICU_IM0_IER;
116 int irq_nr = d->irq - INT_NUM_IRQ0; 124 int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
117 125
118 ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); 126 ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
119 irq_nr %= INT_NUM_IM_OFFSET; 127 offset %= INT_NUM_IM_OFFSET;
120 ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier); 128 ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier);
121} 129}
122 130
123static unsigned int ltq_startup_eiu_irq(struct irq_data *d) 131static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
@@ -126,15 +134,15 @@ static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
126 134
127 ltq_enable_irq(d); 135 ltq_enable_irq(d);
128 for (i = 0; i < MAX_EIU; i++) { 136 for (i = 0; i < MAX_EIU; i++) {
129 if (d->irq == ltq_eiu_irq[i]) { 137 if (d->hwirq == ltq_eiu_irq[i]) {
130 /* low level - we should really handle set_type */ 138 /* low level - we should really handle set_type */
131 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) | 139 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
132 (0x6 << (i * 4)), LTQ_EIU_EXIN_C); 140 (0x6 << (i * 4)), LTQ_EIU_EXIN_C);
133 /* clear all pending */ 141 /* clear all pending */
134 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~(1 << i), 142 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INIC) & ~BIT(i),
135 LTQ_EIU_EXIN_INIC); 143 LTQ_EIU_EXIN_INIC);
136 /* enable */ 144 /* enable */
137 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | (1 << i), 145 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
138 LTQ_EIU_EXIN_INEN); 146 LTQ_EIU_EXIN_INEN);
139 break; 147 break;
140 } 148 }
@@ -149,9 +157,9 @@ static void ltq_shutdown_eiu_irq(struct irq_data *d)
149 157
150 ltq_disable_irq(d); 158 ltq_disable_irq(d);
151 for (i = 0; i < MAX_EIU; i++) { 159 for (i = 0; i < MAX_EIU; i++) {
152 if (d->irq == ltq_eiu_irq[i]) { 160 if (d->hwirq == ltq_eiu_irq[i]) {
153 /* disable */ 161 /* disable */
154 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~(1 << i), 162 ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
155 LTQ_EIU_EXIN_INEN); 163 LTQ_EIU_EXIN_INEN);
156 break; 164 break;
157 } 165 }
@@ -188,14 +196,15 @@ static void ltq_hw_irqdispatch(int module)
188 if (irq == 0) 196 if (irq == 0)
189 return; 197 return;
190 198
191 /* silicon bug causes only the msb set to 1 to be valid. all 199 /*
200 * silicon bug causes only the msb set to 1 to be valid. all
192 * other bits might be bogus 201 * other bits might be bogus
193 */ 202 */
194 irq = __fls(irq); 203 irq = __fls(irq);
195 do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); 204 do_IRQ((int)irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module));
196 205
197 /* if this is a EBU irq, we need to ack it or get a deadlock */ 206 /* if this is a EBU irq, we need to ack it or get a deadlock */
198 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) 207 if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
199 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, 208 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
200 LTQ_EBU_PCC_ISTAT); 209 LTQ_EBU_PCC_ISTAT);
201} 210}
@@ -216,6 +225,47 @@ static void ltq_hw5_irqdispatch(void)
216 do_IRQ(MIPS_CPU_TIMER_IRQ); 225 do_IRQ(MIPS_CPU_TIMER_IRQ);
217} 226}
218 227
228#ifdef CONFIG_MIPS_MT_SMP
229void __init arch_init_ipiirq(int irq, struct irqaction *action)
230{
231 setup_irq(irq, action);
232 irq_set_handler(irq, handle_percpu_irq);
233}
234
235static void ltq_sw0_irqdispatch(void)
236{
237 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
238}
239
240static void ltq_sw1_irqdispatch(void)
241{
242 do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
243}
244static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
245{
246 scheduler_ipi();
247 return IRQ_HANDLED;
248}
249
250static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
251{
252 smp_call_function_interrupt();
253 return IRQ_HANDLED;
254}
255
256static struct irqaction irq_resched = {
257 .handler = ipi_resched_interrupt,
258 .flags = IRQF_PERCPU,
259 .name = "IPI_resched"
260};
261
262static struct irqaction irq_call = {
263 .handler = ipi_call_interrupt,
264 .flags = IRQF_PERCPU,
265 .name = "IPI_call"
266};
267#endif
268
219asmlinkage void plat_irq_dispatch(void) 269asmlinkage void plat_irq_dispatch(void)
220{ 270{
221 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 271 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
@@ -238,45 +288,75 @@ out:
238 return; 288 return;
239} 289}
240 290
291static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
292{
293 struct irq_chip *chip = &ltq_irq_type;
294 int i;
295
296 for (i = 0; i < exin_avail; i++)
297 if (hw == ltq_eiu_irq[i])
298 chip = &ltq_eiu_type;
299
300 irq_set_chip_and_handler(hw, chip, handle_level_irq);
301
302 return 0;
303}
304
305static const struct irq_domain_ops irq_domain_ops = {
306 .xlate = irq_domain_xlate_onetwocell,
307 .map = icu_map,
308};
309
241static struct irqaction cascade = { 310static struct irqaction cascade = {
242 .handler = no_action, 311 .handler = no_action,
243 .name = "cascade", 312 .name = "cascade",
244}; 313};
245 314
246void __init arch_init_irq(void) 315int __init icu_of_init(struct device_node *node, struct device_node *parent)
247{ 316{
317 struct device_node *eiu_node;
318 struct resource res;
248 int i; 319 int i;
249 320
250 if (insert_resource(&iomem_resource, &ltq_icu_resource) < 0) 321 if (of_address_to_resource(node, 0, &res))
251 panic("Failed to insert icu memory"); 322 panic("Failed to get icu memory range");
252 323
253 if (request_mem_region(ltq_icu_resource.start, 324 if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
254 resource_size(&ltq_icu_resource), "icu") < 0) 325 pr_err("Failed to request icu memory");
255 panic("Failed to request icu memory");
256 326
257 ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, 327 ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res));
258 resource_size(&ltq_icu_resource));
259 if (!ltq_icu_membase) 328 if (!ltq_icu_membase)
260 panic("Failed to remap icu memory"); 329 panic("Failed to remap icu memory");
261 330
262 if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0) 331 /* the external interrupts are optional and xway only */
263 panic("Failed to insert eiu memory"); 332 eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
264 333 if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) {
265 if (request_mem_region(ltq_eiu_resource.start, 334 /* find out how many external irq sources we have */
266 resource_size(&ltq_eiu_resource), "eiu") < 0) 335 const __be32 *count = of_get_property(node,
267 panic("Failed to request eiu memory"); 336 "lantiq,count", NULL);
268 337
269 ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, 338 if (count)
270 resource_size(&ltq_eiu_resource)); 339 exin_avail = *count;
271 if (!ltq_eiu_membase) 340 if (exin_avail > MAX_EIU)
272 panic("Failed to remap eiu memory"); 341 exin_avail = MAX_EIU;
342
343 if (request_mem_region(res.start, resource_size(&res),
344 res.name) < 0)
345 pr_err("Failed to request eiu memory");
346
347 ltq_eiu_membase = ioremap_nocache(res.start,
348 resource_size(&res));
349 if (!ltq_eiu_membase)
350 panic("Failed to remap eiu memory");
351 }
273 352
274 /* make sure all irqs are turned off by default */ 353 /* turn off all irqs by default */
275 for (i = 0; i < 5; i++) 354 for (i = 0; i < 5; i++) {
355 /* make sure all irqs are turned off by default */
276 ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); 356 ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
277 357 /* clear all possibly pending interrupts */
278 /* clear all possibly pending interrupts */ 358 ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
279 ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); 359 }
280 360
281 mips_cpu_irq_init(); 361 mips_cpu_irq_init();
282 362
@@ -293,20 +373,19 @@ void __init arch_init_irq(void)
293 set_vi_handler(7, ltq_hw5_irqdispatch); 373 set_vi_handler(7, ltq_hw5_irqdispatch);
294 } 374 }
295 375
296 for (i = INT_NUM_IRQ0; 376 irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET,
297 i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) 377 &irq_domain_ops, 0);
298 if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || 378
299 (i == LTQ_EIU_IR2)) 379#if defined(CONFIG_MIPS_MT_SMP)
300 irq_set_chip_and_handler(i, &ltq_eiu_type, 380 if (cpu_has_vint) {
301 handle_level_irq); 381 pr_info("Setting up IPI vectored interrupts\n");
302 /* EIU3-5 only exist on ar9 and vr9 */ 382 set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
303 else if (((i == LTQ_EIU_IR3) || (i == LTQ_EIU_IR4) || 383 set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
304 (i == LTQ_EIU_IR5)) && (ltq_is_ar9() || ltq_is_vr9())) 384 }
305 irq_set_chip_and_handler(i, &ltq_eiu_type, 385 arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
306 handle_level_irq); 386 &irq_resched);
307 else 387 arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
308 irq_set_chip_and_handler(i, &ltq_irq_type, 388#endif
309 handle_level_irq);
310 389
311#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) 390#if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
312 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | 391 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
@@ -315,9 +394,23 @@ void __init arch_init_irq(void)
315 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | 394 set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
316 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); 395 IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
317#endif 396#endif
397
398 /* tell oprofile which irq to use */
399 cp0_perfcount_irq = LTQ_PERF_IRQ;
400 return 0;
318} 401}
319 402
320unsigned int __cpuinit get_c0_compare_int(void) 403unsigned int __cpuinit get_c0_compare_int(void)
321{ 404{
322 return CP0_LEGACY_COMPARE_IRQ; 405 return CP0_LEGACY_COMPARE_IRQ;
323} 406}
407
408static struct of_device_id __initdata of_irq_ids[] = {
409 { .compatible = "lantiq,icu", .data = icu_of_init },
410 {},
411};
412
413void __init arch_init_irq(void)
414{
415 of_irq_init(of_irq_ids);
416}
diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h
deleted file mode 100644
index 7e01b8c484eb..000000000000
--- a/arch/mips/lantiq/machtypes.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LANTIQ_MACH_H__
10#define _LANTIQ_MACH_H__
11
12#include <asm/mips_machine.h>
13
14enum lantiq_mach_type {
15 LTQ_MACH_GENERIC = 0,
16 LTQ_MACH_EASY50712, /* Danube evaluation board */
17 LTQ_MACH_EASY50601, /* Amazon SE evaluation board */
18};
19
20#endif
diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
index e34fcfd0d5ca..d185e8477fdf 100644
--- a/arch/mips/lantiq/prom.c
+++ b/arch/mips/lantiq/prom.c
@@ -8,6 +8,7 @@
8 8
9#include <linux/export.h> 9#include <linux/export.h>
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/of_platform.h>
11#include <asm/bootinfo.h> 12#include <asm/bootinfo.h>
12#include <asm/time.h> 13#include <asm/time.h>
13 14
@@ -16,19 +17,15 @@
16#include "prom.h" 17#include "prom.h"
17#include "clk.h" 18#include "clk.h"
18 19
19static struct ltq_soc_info soc_info; 20/* access to the ebu needs to be locked between different drivers */
20 21DEFINE_SPINLOCK(ebu_lock);
21unsigned int ltq_get_cpu_ver(void) 22EXPORT_SYMBOL_GPL(ebu_lock);
22{
23 return soc_info.rev;
24}
25EXPORT_SYMBOL(ltq_get_cpu_ver);
26 23
27unsigned int ltq_get_soc_type(void) 24/*
28{ 25 * this struct is filled by the soc specific detection code and holds
29 return soc_info.type; 26 * information about the specific soc type, revision and name
30} 27 */
31EXPORT_SYMBOL(ltq_get_soc_type); 28static struct ltq_soc_info soc_info;
32 29
33const char *get_system_type(void) 30const char *get_system_type(void)
34{ 31{
@@ -45,27 +42,62 @@ static void __init prom_init_cmdline(void)
45 char **argv = (char **) KSEG1ADDR(fw_arg1); 42 char **argv = (char **) KSEG1ADDR(fw_arg1);
46 int i; 43 int i;
47 44
45 arcs_cmdline[0] = '\0';
46
48 for (i = 0; i < argc; i++) { 47 for (i = 0; i < argc; i++) {
49 char *p = (char *) KSEG1ADDR(argv[i]); 48 char *p = (char *) KSEG1ADDR(argv[i]);
50 49
51 if (p && *p) { 50 if (CPHYSADDR(p) && *p) {
52 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); 51 strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
53 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); 52 strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
54 } 53 }
55 } 54 }
56} 55}
57 56
58void __init prom_init(void) 57void __init plat_mem_setup(void)
59{ 58{
60 struct clk *clk; 59 ioport_resource.start = IOPORT_RESOURCE_START;
60 ioport_resource.end = IOPORT_RESOURCE_END;
61 iomem_resource.start = IOMEM_RESOURCE_START;
62 iomem_resource.end = IOMEM_RESOURCE_END;
63
64 set_io_port_base((unsigned long) KSEG1);
61 65
66 /*
67 * Load the builtin devicetree. This causes the chosen node to be
68 * parsed resulting in our memory appearing
69 */
70 __dt_setup_arch(&__dtb_start);
71}
72
73void __init prom_init(void)
74{
75 /* call the soc specific detetcion code and get it to fill soc_info */
62 ltq_soc_detect(&soc_info); 76 ltq_soc_detect(&soc_info);
63 clk_init(); 77 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s",
64 clk = clk_get(0, "cpu"); 78 soc_info.name, soc_info.rev_type);
65 snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d",
66 soc_info.name, soc_info.rev);
67 clk_put(clk);
68 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; 79 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
69 pr_info("SoC: %s\n", soc_info.sys_type); 80 pr_info("SoC: %s\n", soc_info.sys_type);
70 prom_init_cmdline(); 81 prom_init_cmdline();
82
83#if defined(CONFIG_MIPS_MT_SMP)
84 if (register_vsmp_smp_ops())
85 panic("failed to register_vsmp_smp_ops()");
86#endif
71} 87}
88
89int __init plat_of_setup(void)
90{
91 static struct of_device_id of_ids[3];
92
93 if (!of_have_populated_dt())
94 panic("device tree not present");
95
96 strncpy(of_ids[0].compatible, soc_info.compatible,
97 sizeof(of_ids[0].compatible));
98 strncpy(of_ids[1].compatible, "simple-bus",
99 sizeof(of_ids[1].compatible));
100 return of_platform_bus_probe(NULL, of_ids, NULL);
101}
102
103arch_initcall(plat_of_setup);
diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
index b4229d94280f..a3fa1a2bfaae 100644
--- a/arch/mips/lantiq/prom.h
+++ b/arch/mips/lantiq/prom.h
@@ -10,16 +10,22 @@
10#define _LTQ_PROM_H__ 10#define _LTQ_PROM_H__
11 11
12#define LTQ_SYS_TYPE_LEN 0x100 12#define LTQ_SYS_TYPE_LEN 0x100
13#define LTQ_SYS_REV_LEN 0x10
13 14
14struct ltq_soc_info { 15struct ltq_soc_info {
15 unsigned char *name; 16 unsigned char *name;
16 unsigned int rev; 17 unsigned int rev;
18 unsigned char rev_type[LTQ_SYS_REV_LEN];
19 unsigned int srev;
17 unsigned int partnum; 20 unsigned int partnum;
18 unsigned int type; 21 unsigned int type;
19 unsigned char sys_type[LTQ_SYS_TYPE_LEN]; 22 unsigned char sys_type[LTQ_SYS_TYPE_LEN];
23 unsigned char *compatible;
20}; 24};
21 25
22extern void ltq_soc_detect(struct ltq_soc_info *i); 26extern void ltq_soc_detect(struct ltq_soc_info *i);
23extern void ltq_soc_setup(void); 27extern void ltq_soc_init(void);
28
29extern struct boot_param_header __dtb_start;
24 30
25#endif 31#endif
diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c
deleted file mode 100644
index 1ff6c9d6cb93..000000000000
--- a/arch/mips/lantiq/setup.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/kernel.h>
10#include <linux/export.h>
11#include <linux/io.h>
12#include <linux/ioport.h>
13#include <asm/bootinfo.h>
14
15#include <lantiq_soc.h>
16
17#include "machtypes.h"
18#include "devices.h"
19#include "prom.h"
20
21void __init plat_mem_setup(void)
22{
23 /* assume 16M as default incase uboot fails to pass proper ramsize */
24 unsigned long memsize = 16;
25 char **envp = (char **) KSEG1ADDR(fw_arg2);
26
27 ioport_resource.start = IOPORT_RESOURCE_START;
28 ioport_resource.end = IOPORT_RESOURCE_END;
29 iomem_resource.start = IOMEM_RESOURCE_START;
30 iomem_resource.end = IOMEM_RESOURCE_END;
31
32 set_io_port_base((unsigned long) KSEG1);
33
34 while (*envp) {
35 char *e = (char *)KSEG1ADDR(*envp);
36 if (!strncmp(e, "memsize=", 8)) {
37 e += 8;
38 if (strict_strtoul(e, 0, &memsize))
39 pr_warn("bad memsize specified\n");
40 }
41 envp++;
42 }
43 memsize *= 1024 * 1024;
44 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
45}
46
47static int __init
48lantiq_setup(void)
49{
50 ltq_soc_setup();
51 mips_machine_setup();
52 return 0;
53}
54
55arch_initcall(lantiq_setup);
56
57static void __init
58lantiq_generic_init(void)
59{
60 /* Nothing to do */
61}
62
63MIPS_MACHINE(LTQ_MACH_GENERIC,
64 "Generic",
65 "Generic Lantiq based board",
66 lantiq_generic_init);
diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig
deleted file mode 100644
index 2b857de36620..000000000000
--- a/arch/mips/lantiq/xway/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
1if SOC_XWAY
2
3menu "MIPS Machine"
4
5config LANTIQ_MACH_EASY50712
6 bool "Easy50712 - Danube"
7 default y
8
9endmenu
10
11endif
12
13if SOC_AMAZON_SE
14
15menu "MIPS Machine"
16
17config LANTIQ_MACH_EASY50601
18 bool "Easy50601 - Amazon SE"
19 default y
20
21endmenu
22
23endif
diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
index c517f2e77563..dc3194f6ee42 100644
--- a/arch/mips/lantiq/xway/Makefile
+++ b/arch/mips/lantiq/xway/Makefile
@@ -1,7 +1 @@
1obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o
2
3obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
4obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
5
6obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o
7obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o
diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
deleted file mode 100644
index 652258309c9c..000000000000
--- a/arch/mips/lantiq/xway/clk-ase.c
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/io.h>
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/clk.h>
13
14#include <asm/time.h>
15#include <asm/irq.h>
16#include <asm/div64.h>
17
18#include <lantiq_soc.h>
19
20/* cgu registers */
21#define LTQ_CGU_SYS 0x0010
22
23unsigned int ltq_get_io_region_clock(void)
24{
25 return CLOCK_133M;
26}
27EXPORT_SYMBOL(ltq_get_io_region_clock);
28
29unsigned int ltq_get_fpi_bus_clock(int fpi)
30{
31 return CLOCK_133M;
32}
33EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
34
35unsigned int ltq_get_cpu_hz(void)
36{
37 if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
38 return CLOCK_266M;
39 else
40 return CLOCK_133M;
41}
42EXPORT_SYMBOL(ltq_get_cpu_hz);
43
44unsigned int ltq_get_fpi_hz(void)
45{
46 return CLOCK_133M;
47}
48EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
deleted file mode 100644
index 696b1a3e0642..000000000000
--- a/arch/mips/lantiq/xway/clk-xway.c
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/io.h>
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/clk.h>
13
14#include <asm/time.h>
15#include <asm/irq.h>
16#include <asm/div64.h>
17
18#include <lantiq_soc.h>
19
20static unsigned int ltq_ram_clocks[] = {
21 CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
22#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
23
24#define BASIC_FREQUENCY_1 35328000
25#define BASIC_FREQUENCY_2 36000000
26#define BASIS_REQUENCY_USB 12000000
27
28#define GET_BITS(x, msb, lsb) \
29 (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
30
31#define LTQ_CGU_PLL0_CFG 0x0004
32#define LTQ_CGU_PLL1_CFG 0x0008
33#define LTQ_CGU_PLL2_CFG 0x000C
34#define LTQ_CGU_SYS 0x0010
35#define LTQ_CGU_UPDATE 0x0014
36#define LTQ_CGU_IF_CLK 0x0018
37#define LTQ_CGU_OSC_CON 0x001C
38#define LTQ_CGU_SMD 0x0020
39#define LTQ_CGU_CT1SR 0x0028
40#define LTQ_CGU_CT2SR 0x002C
41#define LTQ_CGU_PCMCR 0x0030
42#define LTQ_CGU_PCI_CR 0x0034
43#define LTQ_CGU_PD_PC 0x0038
44#define LTQ_CGU_FMR 0x003C
45
46#define CGU_PLL0_PHASE_DIVIDER_ENABLE \
47 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
48#define CGU_PLL0_BYPASS \
49 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
50#define CGU_PLL0_CFG_DSMSEL \
51 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
52#define CGU_PLL0_CFG_FRAC_EN \
53 (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
54#define CGU_PLL1_SRC \
55 (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
56#define CGU_PLL2_PHASE_DIVIDER_ENABLE \
57 (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
58#define CGU_SYS_FPI_SEL (1 << 6)
59#define CGU_SYS_DDR_SEL 0x3
60#define CGU_PLL0_SRC (1 << 29)
61
62#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
63#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
64#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
65#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
66#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
67
68static unsigned int ltq_get_pll0_fdiv(void);
69
70static inline unsigned int get_input_clock(int pll)
71{
72 switch (pll) {
73 case 0:
74 if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
75 return BASIS_REQUENCY_USB;
76 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
77 return BASIC_FREQUENCY_1;
78 else
79 return BASIC_FREQUENCY_2;
80 case 1:
81 if (CGU_PLL1_SRC)
82 return BASIS_REQUENCY_USB;
83 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
84 return BASIC_FREQUENCY_1;
85 else
86 return BASIC_FREQUENCY_2;
87 case 2:
88 switch (CGU_PLL2_SRC) {
89 case 0:
90 return ltq_get_pll0_fdiv();
91 case 1:
92 return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
93 BASIC_FREQUENCY_1 :
94 BASIC_FREQUENCY_2;
95 case 2:
96 return BASIS_REQUENCY_USB;
97 }
98 default:
99 return 0;
100 }
101}
102
103static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
104{
105 u64 res, clock = get_input_clock(pll);
106
107 res = num * clock;
108 do_div(res, den);
109 return res;
110}
111
112static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
113 unsigned int K)
114{
115 unsigned int num = ((N + 1) << 10) + K;
116 unsigned int den = (M + 1) << 10;
117
118 return cal_dsm(pll, num, den);
119}
120
121static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
122 unsigned int K)
123{
124 unsigned int num = ((N + 1) << 11) + K + 512;
125 unsigned int den = (M + 1) << 11;
126
127 return cal_dsm(pll, num, den);
128}
129
130static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
131 unsigned int K)
132{
133 unsigned int num = K >= 512 ?
134 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
135 unsigned int den = (M + 1) << 12;
136
137 return cal_dsm(pll, num, den);
138}
139
140static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
141 unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
142{
143 if (!dsmsel)
144 return mash_dsm(pll, M, N, K);
145 else if (!phase_div_en)
146 return mash_dsm(pll, M, N, K);
147 else
148 return ssff_dsm_2(pll, M, N, K);
149}
150
151static inline unsigned int ltq_get_pll0_fosc(void)
152{
153 if (CGU_PLL0_BYPASS)
154 return get_input_clock(0);
155 else
156 return !CGU_PLL0_CFG_FRAC_EN
157 ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
158 CGU_PLL0_CFG_DSMSEL,
159 CGU_PLL0_PHASE_DIVIDER_ENABLE)
160 : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
161 CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
162 CGU_PLL0_PHASE_DIVIDER_ENABLE);
163}
164
165static unsigned int ltq_get_pll0_fdiv(void)
166{
167 unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
168
169 return (ltq_get_pll0_fosc() + (div >> 1)) / div;
170}
171
172unsigned int ltq_get_io_region_clock(void)
173{
174 unsigned int ret = ltq_get_pll0_fosc();
175
176 switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
177 default:
178 case 0:
179 return (ret + 1) / 2;
180 case 1:
181 return (ret * 2 + 2) / 5;
182 case 2:
183 return (ret + 1) / 3;
184 case 3:
185 return (ret + 2) / 4;
186 }
187}
188EXPORT_SYMBOL(ltq_get_io_region_clock);
189
190unsigned int ltq_get_fpi_bus_clock(int fpi)
191{
192 unsigned int ret = ltq_get_io_region_clock();
193
194 if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
195 ret >>= 1;
196 return ret;
197}
198EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
199
200unsigned int ltq_get_cpu_hz(void)
201{
202 switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
203 case 0:
204 return CLOCK_333M;
205 case 4:
206 return DDR_HZ;
207 case 8:
208 return DDR_HZ << 1;
209 default:
210 return DDR_HZ >> 1;
211 }
212}
213EXPORT_SYMBOL(ltq_get_cpu_hz);
214
215unsigned int ltq_get_fpi_hz(void)
216{
217 unsigned int ddr_clock = DDR_HZ;
218
219 if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
220 return ddr_clock >> 1;
221 return ddr_clock;
222}
223EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
new file mode 100644
index 000000000000..9aa17f79a742
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk.c
@@ -0,0 +1,151 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/io.h>
10#include <linux/export.h>
11#include <linux/init.h>
12#include <linux/clk.h>
13
14#include <asm/time.h>
15#include <asm/irq.h>
16#include <asm/div64.h>
17
18#include <lantiq_soc.h>
19
20#include "../clk.h"
21
22static unsigned int ram_clocks[] = {
23 CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
24#define DDR_HZ ram_clocks[ltq_cgu_r32(CGU_SYS) & 0x3]
25
26/* legacy xway clock */
27#define CGU_SYS 0x10
28
29/* vr9 clock */
30#define CGU_SYS_VR9 0x0c
31#define CGU_IF_CLK_VR9 0x24
32
33unsigned long ltq_danube_fpi_hz(void)
34{
35 unsigned long ddr_clock = DDR_HZ;
36
37 if (ltq_cgu_r32(CGU_SYS) & 0x40)
38 return ddr_clock >> 1;
39 return ddr_clock;
40}
41
42unsigned long ltq_danube_cpu_hz(void)
43{
44 switch (ltq_cgu_r32(CGU_SYS) & 0xc) {
45 case 0:
46 return CLOCK_333M;
47 case 4:
48 return DDR_HZ;
49 case 8:
50 return DDR_HZ << 1;
51 default:
52 return DDR_HZ >> 1;
53 }
54}
55
56unsigned long ltq_ar9_sys_hz(void)
57{
58 if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
59 return CLOCK_393M;
60 return CLOCK_333M;
61}
62
63unsigned long ltq_ar9_fpi_hz(void)
64{
65 unsigned long sys = ltq_ar9_sys_hz();
66
67 if (ltq_cgu_r32(CGU_SYS) & BIT(0))
68 return sys;
69 return sys >> 1;
70}
71
72unsigned long ltq_ar9_cpu_hz(void)
73{
74 if (ltq_cgu_r32(CGU_SYS) & BIT(2))
75 return ltq_ar9_fpi_hz();
76 else
77 return ltq_ar9_sys_hz();
78}
79
80unsigned long ltq_vr9_cpu_hz(void)
81{
82 unsigned int cpu_sel;
83 unsigned long clk;
84
85 cpu_sel = (ltq_cgu_r32(CGU_SYS_VR9) >> 4) & 0xf;
86
87 switch (cpu_sel) {
88 case 0:
89 clk = CLOCK_600M;
90 break;
91 case 1:
92 clk = CLOCK_500M;
93 break;
94 case 2:
95 clk = CLOCK_393M;
96 break;
97 case 3:
98 clk = CLOCK_333M;
99 break;
100 case 5:
101 case 6:
102 clk = CLOCK_196_608M;
103 break;
104 case 7:
105 clk = CLOCK_167M;
106 break;
107 case 4:
108 case 8:
109 case 9:
110 clk = CLOCK_125M;
111 break;
112 default:
113 clk = 0;
114 break;
115 }
116
117 return clk;
118}
119
120unsigned long ltq_vr9_fpi_hz(void)
121{
122 unsigned int ocp_sel, cpu_clk;
123 unsigned long clk;
124
125 cpu_clk = ltq_vr9_cpu_hz();
126 ocp_sel = ltq_cgu_r32(CGU_SYS_VR9) & 0x3;
127
128 switch (ocp_sel) {
129 case 0:
130 /* OCP ratio 1 */
131 clk = cpu_clk;
132 break;
133 case 2:
134 /* OCP ratio 2 */
135 clk = cpu_clk / 2;
136 break;
137 case 3:
138 /* OCP ratio 2.5 */
139 clk = (cpu_clk * 2) / 5;
140 break;
141 case 4:
142 /* OCP ratio 3 */
143 clk = cpu_clk / 3;
144 break;
145 default:
146 clk = 0;
147 break;
148 }
149
150 return clk;
151}
diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
deleted file mode 100644
index d614aa7ff07f..000000000000
--- a/arch/mips/lantiq/xway/devices.c
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/export.h>
11#include <linux/types.h>
12#include <linux/string.h>
13#include <linux/mtd/physmap.h>
14#include <linux/kernel.h>
15#include <linux/reboot.h>
16#include <linux/platform_device.h>
17#include <linux/leds.h>
18#include <linux/etherdevice.h>
19#include <linux/time.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22
23#include <asm/bootinfo.h>
24#include <asm/irq.h>
25
26#include <lantiq_soc.h>
27#include <lantiq_irq.h>
28#include <lantiq_platform.h>
29
30#include "devices.h"
31
32/* gpio */
33static struct resource ltq_gpio_resource[] = {
34 {
35 .name = "gpio0",
36 .start = LTQ_GPIO0_BASE_ADDR,
37 .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
38 .flags = IORESOURCE_MEM,
39 }, {
40 .name = "gpio1",
41 .start = LTQ_GPIO1_BASE_ADDR,
42 .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
43 .flags = IORESOURCE_MEM,
44 }, {
45 .name = "gpio2",
46 .start = LTQ_GPIO2_BASE_ADDR,
47 .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
48 .flags = IORESOURCE_MEM,
49 }
50};
51
52void __init ltq_register_gpio(void)
53{
54 platform_device_register_simple("ltq_gpio", 0,
55 &ltq_gpio_resource[0], 1);
56 platform_device_register_simple("ltq_gpio", 1,
57 &ltq_gpio_resource[1], 1);
58
59 /* AR9 and VR9 have an extra gpio block */
60 if (ltq_is_ar9() || ltq_is_vr9()) {
61 platform_device_register_simple("ltq_gpio", 2,
62 &ltq_gpio_resource[2], 1);
63 }
64}
65
66/* serial to parallel conversion */
67static struct resource ltq_stp_resource = {
68 .name = "stp",
69 .start = LTQ_STP_BASE_ADDR,
70 .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
71 .flags = IORESOURCE_MEM,
72};
73
74void __init ltq_register_gpio_stp(void)
75{
76 platform_device_register_simple("ltq_stp", 0, &ltq_stp_resource, 1);
77}
78
79/* asc ports - amazon se has its own serial mapping */
80static struct resource ltq_ase_asc_resources[] = {
81 {
82 .name = "asc0",
83 .start = LTQ_ASC1_BASE_ADDR,
84 .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
85 .flags = IORESOURCE_MEM,
86 },
87 IRQ_RES(tx, LTQ_ASC_ASE_TIR),
88 IRQ_RES(rx, LTQ_ASC_ASE_RIR),
89 IRQ_RES(err, LTQ_ASC_ASE_EIR),
90};
91
92void __init ltq_register_ase_asc(void)
93{
94 platform_device_register_simple("ltq_asc", 0,
95 ltq_ase_asc_resources, ARRAY_SIZE(ltq_ase_asc_resources));
96}
97
98/* ethernet */
99static struct resource ltq_etop_resources = {
100 .name = "etop",
101 .start = LTQ_ETOP_BASE_ADDR,
102 .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
103 .flags = IORESOURCE_MEM,
104};
105
106static struct platform_device ltq_etop = {
107 .name = "ltq_etop",
108 .resource = &ltq_etop_resources,
109 .num_resources = 1,
110};
111
112void __init
113ltq_register_etop(struct ltq_eth_data *eth)
114{
115 if (eth) {
116 ltq_etop.dev.platform_data = eth;
117 platform_device_register(&ltq_etop);
118 }
119}
diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h
deleted file mode 100644
index e90493471bc1..000000000000
--- a/arch/mips/lantiq/xway/devices.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#ifndef _LTQ_DEVICES_XWAY_H__
10#define _LTQ_DEVICES_XWAY_H__
11
12#include "../devices.h"
13#include <linux/phy.h>
14
15extern void ltq_register_gpio(void);
16extern void ltq_register_gpio_stp(void);
17extern void ltq_register_ase_asc(void);
18extern void ltq_register_etop(struct ltq_eth_data *eth);
19
20#endif
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
index b210e936c7c3..55d2c4fa4714 100644
--- a/arch/mips/lantiq/xway/dma.c
+++ b/arch/mips/lantiq/xway/dma.c
@@ -19,7 +19,8 @@
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/dma-mapping.h> 21#include <linux/dma-mapping.h>
22#include <linux/export.h> 22#include <linux/module.h>
23#include <linux/clk.h>
23 24
24#include <lantiq_soc.h> 25#include <lantiq_soc.h>
25#include <xway_dma.h> 26#include <xway_dma.h>
@@ -55,13 +56,6 @@
55#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ 56#define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \
56 ltq_dma_membase + (z)) 57 ltq_dma_membase + (z))
57 58
58static struct resource ltq_dma_resource = {
59 .name = "dma",
60 .start = LTQ_DMA_BASE_ADDR,
61 .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1,
62 .flags = IORESOURCE_MEM,
63};
64
65static void __iomem *ltq_dma_membase; 59static void __iomem *ltq_dma_membase;
66 60
67void 61void
@@ -215,27 +209,28 @@ ltq_dma_init_port(int p)
215} 209}
216EXPORT_SYMBOL_GPL(ltq_dma_init_port); 210EXPORT_SYMBOL_GPL(ltq_dma_init_port);
217 211
218int __init 212static int __devinit
219ltq_dma_init(void) 213ltq_dma_init(struct platform_device *pdev)
220{ 214{
215 struct clk *clk;
216 struct resource *res;
221 int i; 217 int i;
222 218
223 /* insert and request the memory region */ 219 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224 if (insert_resource(&iomem_resource, &ltq_dma_resource) < 0) 220 if (!res)
225 panic("Failed to insert dma memory"); 221 panic("Failed to get dma resource");
226
227 if (request_mem_region(ltq_dma_resource.start,
228 resource_size(&ltq_dma_resource), "dma") < 0)
229 panic("Failed to request dma memory");
230 222
231 /* remap dma register range */ 223 /* remap dma register range */
232 ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, 224 ltq_dma_membase = devm_request_and_ioremap(&pdev->dev, res);
233 resource_size(&ltq_dma_resource));
234 if (!ltq_dma_membase) 225 if (!ltq_dma_membase)
235 panic("Failed to remap dma memory"); 226 panic("Failed to remap dma resource");
236 227
237 /* power up and reset the dma engine */ 228 /* power up and reset the dma engine */
238 ltq_pmu_enable(PMU_DMA); 229 clk = clk_get(&pdev->dev, NULL);
230 if (IS_ERR(clk))
231 panic("Failed to get dma clock");
232
233 clk_enable(clk);
239 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); 234 ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL);
240 235
241 /* disable all interrupts */ 236 /* disable all interrupts */
@@ -248,7 +243,29 @@ ltq_dma_init(void)
248 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL); 243 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
249 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL); 244 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
250 } 245 }
246 dev_info(&pdev->dev, "init done\n");
251 return 0; 247 return 0;
252} 248}
253 249
254postcore_initcall(ltq_dma_init); 250static const struct of_device_id dma_match[] = {
251 { .compatible = "lantiq,dma-xway" },
252 {},
253};
254MODULE_DEVICE_TABLE(of, dma_match);
255
256static struct platform_driver dma_driver = {
257 .probe = ltq_dma_init,
258 .driver = {
259 .name = "dma-xway",
260 .owner = THIS_MODULE,
261 .of_match_table = dma_match,
262 },
263};
264
265int __init
266dma_init(void)
267{
268 return platform_driver_register(&dma_driver);
269}
270
271postcore_initcall(dma_init);
diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
deleted file mode 100644
index 862e3e830680..000000000000
--- a/arch/mips/lantiq/xway/ebu.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * EBU - the external bus unit attaches PCI, NOR and NAND
7 *
8 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/ioport.h>
14
15#include <lantiq_soc.h>
16
17/* all access to the ebu must be locked */
18DEFINE_SPINLOCK(ebu_lock);
19EXPORT_SYMBOL_GPL(ebu_lock);
20
21static struct resource ltq_ebu_resource = {
22 .name = "ebu",
23 .start = LTQ_EBU_BASE_ADDR,
24 .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
25 .flags = IORESOURCE_MEM,
26};
27
28/* remapped base addr of the clock unit and external bus unit */
29void __iomem *ltq_ebu_membase;
30
31static int __init lantiq_ebu_init(void)
32{
33 /* insert and request the memory region */
34 if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
35 panic("Failed to insert ebu memory");
36
37 if (request_mem_region(ltq_ebu_resource.start,
38 resource_size(&ltq_ebu_resource), "ebu") < 0)
39 panic("Failed to request ebu memory");
40
41 /* remap ebu register range */
42 ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
43 resource_size(&ltq_ebu_resource));
44 if (!ltq_ebu_membase)
45 panic("Failed to remap ebu memory");
46
47 /* make sure to unprotect the memory region where flash is located */
48 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
49 return 0;
50}
51
52postcore_initcall(lantiq_ebu_init);
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
index c429a5bc080f..2ab39e93d9be 100644
--- a/arch/mips/lantiq/xway/gpio.c
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -36,18 +36,6 @@ struct ltq_gpio {
36 36
37static struct ltq_gpio ltq_gpio_port[MAX_PORTS]; 37static struct ltq_gpio ltq_gpio_port[MAX_PORTS];
38 38
39int gpio_to_irq(unsigned int gpio)
40{
41 return -EINVAL;
42}
43EXPORT_SYMBOL(gpio_to_irq);
44
45int irq_to_gpio(unsigned int gpio)
46{
47 return -EINVAL;
48}
49EXPORT_SYMBOL(irq_to_gpio);
50
51int ltq_gpio_request(unsigned int pin, unsigned int alt0, 39int ltq_gpio_request(unsigned int pin, unsigned int alt0,
52 unsigned int alt1, unsigned int dir, const char *name) 40 unsigned int alt1, unsigned int dir, const char *name)
53{ 41{
diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c
deleted file mode 100644
index aae17170472f..000000000000
--- a/arch/mips/lantiq/xway/gpio_ebu.c
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/export.h>
11#include <linux/types.h>
12#include <linux/platform_device.h>
13#include <linux/mutex.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16
17#include <lantiq_soc.h>
18
19/*
20 * By attaching hardware latches to the EBU it is possible to create output
21 * only gpios. This driver configures a special memory address, which when
22 * written to outputs 16 bit to the latches.
23 */
24
25#define LTQ_EBU_BUSCON 0x1e7ff /* 16 bit access, slowest timing */
26#define LTQ_EBU_WP 0x80000000 /* write protect bit */
27
28/* we keep a shadow value of the last value written to the ebu */
29static int ltq_ebu_gpio_shadow = 0x0;
30static void __iomem *ltq_ebu_gpio_membase;
31
32static void ltq_ebu_apply(void)
33{
34 unsigned long flags;
35
36 spin_lock_irqsave(&ebu_lock, flags);
37 ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
38 *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow;
39 ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
40 spin_unlock_irqrestore(&ebu_lock, flags);
41}
42
43static void ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
44{
45 if (value)
46 ltq_ebu_gpio_shadow |= (1 << offset);
47 else
48 ltq_ebu_gpio_shadow &= ~(1 << offset);
49 ltq_ebu_apply();
50}
51
52static int ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset,
53 int value)
54{
55 ltq_ebu_set(chip, offset, value);
56
57 return 0;
58}
59
60static struct gpio_chip ltq_ebu_chip = {
61 .label = "ltq_ebu",
62 .direction_output = ltq_ebu_direction_output,
63 .set = ltq_ebu_set,
64 .base = 72,
65 .ngpio = 16,
66 .can_sleep = 1,
67 .owner = THIS_MODULE,
68};
69
70static int ltq_ebu_probe(struct platform_device *pdev)
71{
72 int ret = 0;
73 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
74
75 if (!res) {
76 dev_err(&pdev->dev, "failed to get memory resource\n");
77 return -ENOENT;
78 }
79
80 res = devm_request_mem_region(&pdev->dev, res->start,
81 resource_size(res), dev_name(&pdev->dev));
82 if (!res) {
83 dev_err(&pdev->dev, "failed to request memory resource\n");
84 return -EBUSY;
85 }
86
87 ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start,
88 resource_size(res));
89 if (!ltq_ebu_gpio_membase) {
90 dev_err(&pdev->dev, "Failed to ioremap mem region\n");
91 return -ENOMEM;
92 }
93
94 /* grab the default shadow value passed form the platform code */
95 ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data;
96
97 /* tell the ebu controller which memory address we will be using */
98 ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1);
99
100 /* write protect the region */
101 ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
102
103 ret = gpiochip_add(&ltq_ebu_chip);
104 if (!ret)
105 ltq_ebu_apply();
106 return ret;
107}
108
109static struct platform_driver ltq_ebu_driver = {
110 .probe = ltq_ebu_probe,
111 .driver = {
112 .name = "ltq_ebu",
113 .owner = THIS_MODULE,
114 },
115};
116
117static int __init ltq_ebu_init(void)
118{
119 int ret = platform_driver_register(&ltq_ebu_driver);
120
121 if (ret)
122 pr_info("ltq_ebu : Error registering platform driver!");
123 return ret;
124}
125
126postcore_initcall(ltq_ebu_init);
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
deleted file mode 100644
index fd07d87adaa9..000000000000
--- a/arch/mips/lantiq/xway/gpio_stp.c
+++ /dev/null
@@ -1,157 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
7 *
8 */
9
10#include <linux/slab.h>
11#include <linux/init.h>
12#include <linux/export.h>
13#include <linux/types.h>
14#include <linux/platform_device.h>
15#include <linux/mutex.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18
19#include <lantiq_soc.h>
20
21#define LTQ_STP_CON0 0x00
22#define LTQ_STP_CON1 0x04
23#define LTQ_STP_CPU0 0x08
24#define LTQ_STP_CPU1 0x0C
25#define LTQ_STP_AR 0x10
26
27#define LTQ_STP_CON_SWU (1 << 31)
28#define LTQ_STP_2HZ 0
29#define LTQ_STP_4HZ (1 << 23)
30#define LTQ_STP_8HZ (2 << 23)
31#define LTQ_STP_10HZ (3 << 23)
32#define LTQ_STP_SPEED_MASK (0xf << 23)
33#define LTQ_STP_UPD_FPI (1 << 31)
34#define LTQ_STP_UPD_MASK (3 << 30)
35#define LTQ_STP_ADSL_SRC (3 << 24)
36
37#define LTQ_STP_GROUP0 (1 << 0)
38
39#define LTQ_STP_RISING 0
40#define LTQ_STP_FALLING (1 << 26)
41#define LTQ_STP_EDGE_MASK (1 << 26)
42
43#define ltq_stp_r32(reg) __raw_readl(ltq_stp_membase + reg)
44#define ltq_stp_w32(val, reg) __raw_writel(val, ltq_stp_membase + reg)
45#define ltq_stp_w32_mask(clear, set, reg) \
46 ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \
47 ltq_stp_membase + (reg))
48
49static int ltq_stp_shadow = 0xffff;
50static void __iomem *ltq_stp_membase;
51
52static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
53{
54 if (value)
55 ltq_stp_shadow |= (1 << offset);
56 else
57 ltq_stp_shadow &= ~(1 << offset);
58 ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
59}
60
61static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
62 int value)
63{
64 ltq_stp_set(chip, offset, value);
65
66 return 0;
67}
68
69static struct gpio_chip ltq_stp_chip = {
70 .label = "ltq_stp",
71 .direction_output = ltq_stp_direction_output,
72 .set = ltq_stp_set,
73 .base = 48,
74 .ngpio = 24,
75 .can_sleep = 1,
76 .owner = THIS_MODULE,
77};
78
79static int ltq_stp_hw_init(void)
80{
81 /* the 3 pins used to control the external stp */
82 ltq_gpio_request(4, 1, 0, 1, "stp-st");
83 ltq_gpio_request(5, 1, 0, 1, "stp-d");
84 ltq_gpio_request(6, 1, 0, 1, "stp-sh");
85
86 /* sane defaults */
87 ltq_stp_w32(0, LTQ_STP_AR);
88 ltq_stp_w32(0, LTQ_STP_CPU0);
89 ltq_stp_w32(0, LTQ_STP_CPU1);
90 ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0);
91 ltq_stp_w32(0, LTQ_STP_CON1);
92
93 /* rising or falling edge */
94 ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
95
96 /* per default stp 15-0 are set */
97 ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
98
99 /* stp are update periodically by the FPI bus */
100 ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
101
102 /* set stp update speed */
103 ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
104
105 /* tell the hardware that pin (led) 0 and 1 are controlled
106 * by the dsl arc
107 */
108 ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
109
110 ltq_pmu_enable(PMU_LED);
111 return 0;
112}
113
114static int __devinit ltq_stp_probe(struct platform_device *pdev)
115{
116 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
117 int ret = 0;
118
119 if (!res)
120 return -ENOENT;
121 res = devm_request_mem_region(&pdev->dev, res->start,
122 resource_size(res), dev_name(&pdev->dev));
123 if (!res) {
124 dev_err(&pdev->dev, "failed to request STP memory\n");
125 return -EBUSY;
126 }
127 ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start,
128 resource_size(res));
129 if (!ltq_stp_membase) {
130 dev_err(&pdev->dev, "failed to remap STP memory\n");
131 return -ENOMEM;
132 }
133 ret = gpiochip_add(&ltq_stp_chip);
134 if (!ret)
135 ret = ltq_stp_hw_init();
136
137 return ret;
138}
139
140static struct platform_driver ltq_stp_driver = {
141 .probe = ltq_stp_probe,
142 .driver = {
143 .name = "ltq_stp",
144 .owner = THIS_MODULE,
145 },
146};
147
148int __init ltq_stp_init(void)
149{
150 int ret = platform_driver_register(&ltq_stp_driver);
151
152 if (ret)
153 pr_info("ltq_stp: error registering platform driver");
154 return ret;
155}
156
157postcore_initcall(ltq_stp_init);
diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c
deleted file mode 100644
index d5aaf637ab19..000000000000
--- a/arch/mips/lantiq/xway/mach-easy50601.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/input.h>
15
16#include <lantiq.h>
17
18#include "../machtypes.h"
19#include "devices.h"
20
21static struct mtd_partition easy50601_partitions[] = {
22 {
23 .name = "uboot",
24 .offset = 0x0,
25 .size = 0x10000,
26 },
27 {
28 .name = "uboot_env",
29 .offset = 0x10000,
30 .size = 0x10000,
31 },
32 {
33 .name = "linux",
34 .offset = 0x20000,
35 .size = 0xE0000,
36 },
37 {
38 .name = "rootfs",
39 .offset = 0x100000,
40 .size = 0x300000,
41 },
42};
43
44static struct physmap_flash_data easy50601_flash_data = {
45 .nr_parts = ARRAY_SIZE(easy50601_partitions),
46 .parts = easy50601_partitions,
47};
48
49static void __init easy50601_init(void)
50{
51 ltq_register_nor(&easy50601_flash_data);
52}
53
54MIPS_MACHINE(LTQ_MACH_EASY50601,
55 "EASY50601",
56 "EASY50601 Eval Board",
57 easy50601_init);
diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c
deleted file mode 100644
index ea5027b3239d..000000000000
--- a/arch/mips/lantiq/xway/mach-easy50712.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/partitions.h>
13#include <linux/mtd/physmap.h>
14#include <linux/input.h>
15#include <linux/phy.h>
16
17#include <lantiq_soc.h>
18#include <irq.h>
19
20#include "../machtypes.h"
21#include "devices.h"
22
23static struct mtd_partition easy50712_partitions[] = {
24 {
25 .name = "uboot",
26 .offset = 0x0,
27 .size = 0x10000,
28 },
29 {
30 .name = "uboot_env",
31 .offset = 0x10000,
32 .size = 0x10000,
33 },
34 {
35 .name = "linux",
36 .offset = 0x20000,
37 .size = 0xe0000,
38 },
39 {
40 .name = "rootfs",
41 .offset = 0x100000,
42 .size = 0x300000,
43 },
44};
45
46static struct physmap_flash_data easy50712_flash_data = {
47 .nr_parts = ARRAY_SIZE(easy50712_partitions),
48 .parts = easy50712_partitions,
49};
50
51static struct ltq_pci_data ltq_pci_data = {
52 .clock = PCI_CLOCK_INT,
53 .gpio = PCI_GNT1 | PCI_REQ1,
54 .irq = {
55 [14] = INT_NUM_IM0_IRL0 + 22,
56 },
57};
58
59static struct ltq_eth_data ltq_eth_data = {
60 .mii_mode = PHY_INTERFACE_MODE_MII,
61};
62
63static void __init easy50712_init(void)
64{
65 ltq_register_gpio_stp();
66 ltq_register_nor(&easy50712_flash_data);
67 ltq_register_pci(&ltq_pci_data);
68 ltq_register_etop(&ltq_eth_data);
69}
70
71MIPS_MACHINE(LTQ_MACH_EASY50712,
72 "EASY50712",
73 "EASY50712 Eval Board",
74 easy50712_init);
diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
deleted file mode 100644
index fe85361e032e..000000000000
--- a/arch/mips/lantiq/xway/pmu.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/ioport.h>
12
13#include <lantiq_soc.h>
14
15/* PMU - the power management unit allows us to turn part of the core
16 * on and off
17 */
18
19/* the enable / disable registers */
20#define LTQ_PMU_PWDCR 0x1C
21#define LTQ_PMU_PWDSR 0x20
22
23#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y))
24#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x))
25
26static struct resource ltq_pmu_resource = {
27 .name = "pmu",
28 .start = LTQ_PMU_BASE_ADDR,
29 .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
30 .flags = IORESOURCE_MEM,
31};
32
33static void __iomem *ltq_pmu_membase;
34
35void ltq_pmu_enable(unsigned int module)
36{
37 int err = 1000000;
38
39 ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
40 do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
41
42 if (!err)
43 panic("activating PMU module failed!");
44}
45EXPORT_SYMBOL(ltq_pmu_enable);
46
47void ltq_pmu_disable(unsigned int module)
48{
49 ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
50}
51EXPORT_SYMBOL(ltq_pmu_disable);
52
53int __init ltq_pmu_init(void)
54{
55 if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
56 panic("Failed to insert pmu memory");
57
58 if (request_mem_region(ltq_pmu_resource.start,
59 resource_size(&ltq_pmu_resource), "pmu") < 0)
60 panic("Failed to request pmu memory");
61
62 ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
63 resource_size(&ltq_pmu_resource));
64 if (!ltq_pmu_membase)
65 panic("Failed to remap pmu memory");
66 return 0;
67}
68
69core_initcall(ltq_pmu_init);
diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
deleted file mode 100644
index ae4959ae865c..000000000000
--- a/arch/mips/lantiq/xway/prom-ase.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/export.h>
10#include <linux/clk.h>
11#include <asm/bootinfo.h>
12#include <asm/time.h>
13
14#include <lantiq_soc.h>
15
16#include "../prom.h"
17
18#define SOC_AMAZON_SE "Amazon_SE"
19
20#define PART_SHIFT 12
21#define PART_MASK 0x0FFFFFFF
22#define REV_SHIFT 28
23#define REV_MASK 0xF0000000
24
25void __init ltq_soc_detect(struct ltq_soc_info *i)
26{
27 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
28 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
29 switch (i->partnum) {
30 case SOC_ID_AMAZON_SE:
31 i->name = SOC_AMAZON_SE;
32 i->type = SOC_TYPE_AMAZON_SE;
33 break;
34
35 default:
36 unreachable();
37 break;
38 }
39}
diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
deleted file mode 100644
index 2228133ca356..000000000000
--- a/arch/mips/lantiq/xway/prom-xway.c
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/export.h>
10#include <linux/clk.h>
11#include <asm/bootinfo.h>
12#include <asm/time.h>
13
14#include <lantiq_soc.h>
15
16#include "../prom.h"
17
18#define SOC_DANUBE "Danube"
19#define SOC_TWINPASS "Twinpass"
20#define SOC_AR9 "AR9"
21
22#define PART_SHIFT 12
23#define PART_MASK 0x0FFFFFFF
24#define REV_SHIFT 28
25#define REV_MASK 0xF0000000
26
27void __init ltq_soc_detect(struct ltq_soc_info *i)
28{
29 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
30 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
31 switch (i->partnum) {
32 case SOC_ID_DANUBE1:
33 case SOC_ID_DANUBE2:
34 i->name = SOC_DANUBE;
35 i->type = SOC_TYPE_DANUBE;
36 break;
37
38 case SOC_ID_TWINPASS:
39 i->name = SOC_TWINPASS;
40 i->type = SOC_TYPE_DANUBE;
41 break;
42
43 case SOC_ID_ARX188:
44 case SOC_ID_ARX168:
45 case SOC_ID_ARX182:
46 i->name = SOC_AR9;
47 i->type = SOC_TYPE_AR9;
48 break;
49
50 default:
51 unreachable();
52 break;
53 }
54}
diff --git a/arch/mips/lantiq/xway/prom.c b/arch/mips/lantiq/xway/prom.c
new file mode 100644
index 000000000000..248429ab2622
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom.c
@@ -0,0 +1,115 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/export.h>
10#include <linux/clk.h>
11#include <asm/bootinfo.h>
12#include <asm/time.h>
13
14#include <lantiq_soc.h>
15
16#include "../prom.h"
17
18#define SOC_DANUBE "Danube"
19#define SOC_TWINPASS "Twinpass"
20#define SOC_AMAZON_SE "Amazon_SE"
21#define SOC_AR9 "AR9"
22#define SOC_GR9 "GR9"
23#define SOC_VR9 "VR9"
24
25#define COMP_DANUBE "lantiq,danube"
26#define COMP_TWINPASS "lantiq,twinpass"
27#define COMP_AMAZON_SE "lantiq,ase"
28#define COMP_AR9 "lantiq,ar9"
29#define COMP_GR9 "lantiq,gr9"
30#define COMP_VR9 "lantiq,vr9"
31
32#define PART_SHIFT 12
33#define PART_MASK 0x0FFFFFFF
34#define REV_SHIFT 28
35#define REV_MASK 0xF0000000
36
37void __init ltq_soc_detect(struct ltq_soc_info *i)
38{
39 i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
40 i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
41 sprintf(i->rev_type, "1.%d", i->rev);
42 switch (i->partnum) {
43 case SOC_ID_DANUBE1:
44 case SOC_ID_DANUBE2:
45 i->name = SOC_DANUBE;
46 i->type = SOC_TYPE_DANUBE;
47 i->compatible = COMP_DANUBE;
48 break;
49
50 case SOC_ID_TWINPASS:
51 i->name = SOC_TWINPASS;
52 i->type = SOC_TYPE_DANUBE;
53 i->compatible = COMP_TWINPASS;
54 break;
55
56 case SOC_ID_ARX188:
57 case SOC_ID_ARX168_1:
58 case SOC_ID_ARX168_2:
59 case SOC_ID_ARX182:
60 i->name = SOC_AR9;
61 i->type = SOC_TYPE_AR9;
62 i->compatible = COMP_AR9;
63 break;
64
65 case SOC_ID_GRX188:
66 case SOC_ID_GRX168:
67 i->name = SOC_GR9;
68 i->type = SOC_TYPE_AR9;
69 i->compatible = COMP_GR9;
70 break;
71
72 case SOC_ID_AMAZON_SE_1:
73 case SOC_ID_AMAZON_SE_2:
74#ifdef CONFIG_PCI
75 panic("ase is only supported for non pci kernels");
76#endif
77 i->name = SOC_AMAZON_SE;
78 i->type = SOC_TYPE_AMAZON_SE;
79 i->compatible = COMP_AMAZON_SE;
80 break;
81
82 case SOC_ID_VRX282:
83 case SOC_ID_VRX268:
84 case SOC_ID_VRX288:
85 i->name = SOC_VR9;
86 i->type = SOC_TYPE_VR9;
87 i->compatible = COMP_VR9;
88 break;
89
90 case SOC_ID_GRX268:
91 case SOC_ID_GRX288:
92 i->name = SOC_GR9;
93 i->type = SOC_TYPE_VR9;
94 i->compatible = COMP_GR9;
95 break;
96
97 case SOC_ID_VRX268_2:
98 case SOC_ID_VRX288_2:
99 i->name = SOC_VR9;
100 i->type = SOC_TYPE_VR9_2;
101 i->compatible = COMP_VR9;
102 break;
103
104 case SOC_ID_GRX282_2:
105 case SOC_ID_GRX288_2:
106 i->name = SOC_GR9;
107 i->type = SOC_TYPE_VR9_2;
108 i->compatible = COMP_GR9;
109 break;
110
111 default:
112 unreachable();
113 break;
114 }
115}
diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
index 8b66bd87f0c1..22c55f73aa9d 100644
--- a/arch/mips/lantiq/xway/reset.c
+++ b/arch/mips/lantiq/xway/reset.c
@@ -11,26 +11,31 @@
11#include <linux/ioport.h> 11#include <linux/ioport.h>
12#include <linux/pm.h> 12#include <linux/pm.h>
13#include <linux/export.h> 13#include <linux/export.h>
14#include <linux/delay.h>
15#include <linux/of_address.h>
16#include <linux/of_platform.h>
17
14#include <asm/reboot.h> 18#include <asm/reboot.h>
15 19
16#include <lantiq_soc.h> 20#include <lantiq_soc.h>
17 21
22#include "../prom.h"
23
18#define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) 24#define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y))
19#define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) 25#define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x))
20 26
21/* register definitions */ 27/* reset request register */
22#define LTQ_RCU_RST 0x0010 28#define RCU_RST_REQ 0x0010
23#define LTQ_RCU_RST_ALL 0x40000000 29/* reset status register */
24 30#define RCU_RST_STAT 0x0014
25#define LTQ_RCU_RST_STAT 0x0014
26#define LTQ_RCU_STAT_SHIFT 26
27 31
28static struct resource ltq_rcu_resource = { 32/* reboot bit */
29 .name = "rcu", 33#define RCU_RD_SRST BIT(30)
30 .start = LTQ_RCU_BASE_ADDR, 34/* reset cause */
31 .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1, 35#define RCU_STAT_SHIFT 26
32 .flags = IORESOURCE_MEM, 36/* boot selection */
33}; 37#define RCU_BOOT_SEL_SHIFT 26
38#define RCU_BOOT_SEL_MASK 0x7
34 39
35/* remapped base addr of the reset control unit */ 40/* remapped base addr of the reset control unit */
36static void __iomem *ltq_rcu_membase; 41static void __iomem *ltq_rcu_membase;
@@ -38,48 +43,64 @@ static void __iomem *ltq_rcu_membase;
38/* This function is used by the watchdog driver */ 43/* This function is used by the watchdog driver */
39int ltq_reset_cause(void) 44int ltq_reset_cause(void)
40{ 45{
41 u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT); 46 u32 val = ltq_rcu_r32(RCU_RST_STAT);
42 return val >> LTQ_RCU_STAT_SHIFT; 47 return val >> RCU_STAT_SHIFT;
43} 48}
44EXPORT_SYMBOL_GPL(ltq_reset_cause); 49EXPORT_SYMBOL_GPL(ltq_reset_cause);
45 50
51/* allow platform code to find out what source we booted from */
52unsigned char ltq_boot_select(void)
53{
54 u32 val = ltq_rcu_r32(RCU_RST_STAT);
55 return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK;
56}
57
58/* reset a io domain for u micro seconds */
59void ltq_reset_once(unsigned int module, ulong u)
60{
61 ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
62 udelay(u);
63 ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
64}
65
46static void ltq_machine_restart(char *command) 66static void ltq_machine_restart(char *command)
47{ 67{
48 pr_notice("System restart\n");
49 local_irq_disable(); 68 local_irq_disable();
50 ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST); 69 ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ);
51 unreachable(); 70 unreachable();
52} 71}
53 72
54static void ltq_machine_halt(void) 73static void ltq_machine_halt(void)
55{ 74{
56 pr_notice("System halted.\n");
57 local_irq_disable(); 75 local_irq_disable();
58 unreachable(); 76 unreachable();
59} 77}
60 78
61static void ltq_machine_power_off(void) 79static void ltq_machine_power_off(void)
62{ 80{
63 pr_notice("Please turn off the power now.\n");
64 local_irq_disable(); 81 local_irq_disable();
65 unreachable(); 82 unreachable();
66} 83}
67 84
68static int __init mips_reboot_setup(void) 85static int __init mips_reboot_setup(void)
69{ 86{
70 /* insert and request the memory region */ 87 struct resource res;
71 if (insert_resource(&iomem_resource, &ltq_rcu_resource) < 0) 88 struct device_node *np =
72 panic("Failed to insert rcu memory"); 89 of_find_compatible_node(NULL, NULL, "lantiq,rcu-xway");
90
91 /* check if all the reset register range is available */
92 if (!np)
93 panic("Failed to load reset resources from devicetree");
94
95 if (of_address_to_resource(np, 0, &res))
96 panic("Failed to get rcu memory range");
73 97
74 if (request_mem_region(ltq_rcu_resource.start, 98 if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
75 resource_size(&ltq_rcu_resource), "rcu") < 0) 99 pr_err("Failed to request rcu memory");
76 panic("Failed to request rcu memory");
77 100
78 /* remap rcu register range */ 101 ltq_rcu_membase = ioremap_nocache(res.start, resource_size(&res));
79 ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start,
80 resource_size(&ltq_rcu_resource));
81 if (!ltq_rcu_membase) 102 if (!ltq_rcu_membase)
82 panic("Failed to remap rcu memory"); 103 panic("Failed to remap core memory");
83 104
84 _machine_restart = ltq_machine_restart; 105 _machine_restart = ltq_machine_restart;
85 _machine_halt = ltq_machine_halt; 106 _machine_halt = ltq_machine_halt;
diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
deleted file mode 100644
index f6f326798a39..000000000000
--- a/arch/mips/lantiq/xway/setup-ase.c
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
7 */
8
9#include <lantiq_soc.h>
10
11#include "../prom.h"
12#include "devices.h"
13
14void __init ltq_soc_setup(void)
15{
16 ltq_register_ase_asc();
17 ltq_register_gpio();
18 ltq_register_wdt();
19}
diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
deleted file mode 100644
index c292f643a858..000000000000
--- a/arch/mips/lantiq/xway/setup-xway.c
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
7 */
8
9#include <lantiq_soc.h>
10
11#include "../prom.h"
12#include "devices.h"
13
14void __init ltq_soc_setup(void)
15{
16 ltq_register_asc(0);
17 ltq_register_asc(1);
18 ltq_register_gpio();
19 ltq_register_wdt();
20}
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
new file mode 100644
index 000000000000..83780f7c842b
--- /dev/null
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -0,0 +1,371 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2011-2012 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/ioport.h>
10#include <linux/export.h>
11#include <linux/clkdev.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <linux/of_address.h>
15
16#include <lantiq_soc.h>
17
18#include "../clk.h"
19#include "../prom.h"
20
21/* clock control register */
22#define CGU_IFCCR 0x0018
23/* system clock register */
24#define CGU_SYS 0x0010
25/* pci control register */
26#define CGU_PCICR 0x0034
27/* ephy configuration register */
28#define CGU_EPHY 0x10
29/* power control register */
30#define PMU_PWDCR 0x1C
31/* power status register */
32#define PMU_PWDSR 0x20
33/* power control register */
34#define PMU_PWDCR1 0x24
35/* power status register */
36#define PMU_PWDSR1 0x28
37/* power control register */
38#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
39/* power status register */
40#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
41
42/* clock gates that we can en/disable */
43#define PMU_USB0_P BIT(0)
44#define PMU_PCI BIT(4)
45#define PMU_DMA BIT(5)
46#define PMU_USB0 BIT(6)
47#define PMU_ASC0 BIT(7)
48#define PMU_EPHY BIT(7) /* ase */
49#define PMU_SPI BIT(8)
50#define PMU_DFE BIT(9)
51#define PMU_EBU BIT(10)
52#define PMU_STP BIT(11)
53#define PMU_GPT BIT(12)
54#define PMU_AHBS BIT(13) /* vr9 */
55#define PMU_FPI BIT(14)
56#define PMU_AHBM BIT(15)
57#define PMU_ASC1 BIT(17)
58#define PMU_PPE_QSB BIT(18)
59#define PMU_PPE_SLL01 BIT(19)
60#define PMU_PPE_TC BIT(21)
61#define PMU_PPE_EMA BIT(22)
62#define PMU_PPE_DPLUM BIT(23)
63#define PMU_PPE_DPLUS BIT(24)
64#define PMU_USB1_P BIT(26)
65#define PMU_USB1 BIT(27)
66#define PMU_SWITCH BIT(28)
67#define PMU_PPE_TOP BIT(29)
68#define PMU_GPHY BIT(30)
69#define PMU_PCIE_CLK BIT(31)
70
71#define PMU1_PCIE_PHY BIT(0)
72#define PMU1_PCIE_CTL BIT(1)
73#define PMU1_PCIE_PDI BIT(4)
74#define PMU1_PCIE_MSI BIT(5)
75
76#define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
77#define pmu_r32(x) ltq_r32(pmu_membase + (x))
78
79static void __iomem *pmu_membase;
80void __iomem *ltq_cgu_membase;
81void __iomem *ltq_ebu_membase;
82
83/* legacy function kept alive to ease clkdev transition */
84void ltq_pmu_enable(unsigned int module)
85{
86 int err = 1000000;
87
88 pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
89 do {} while (--err && (pmu_r32(PMU_PWDSR) & module));
90
91 if (!err)
92 panic("activating PMU module failed!");
93}
94EXPORT_SYMBOL(ltq_pmu_enable);
95
96/* legacy function kept alive to ease clkdev transition */
97void ltq_pmu_disable(unsigned int module)
98{
99 pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
100}
101EXPORT_SYMBOL(ltq_pmu_disable);
102
103/* enable a hw clock */
104static int cgu_enable(struct clk *clk)
105{
106 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR);
107 return 0;
108}
109
110/* disable a hw clock */
111static void cgu_disable(struct clk *clk)
112{
113 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR);
114}
115
116/* enable a clock gate */
117static int pmu_enable(struct clk *clk)
118{
119 int retry = 1000000;
120
121 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
122 PWDCR(clk->module));
123 do {} while (--retry && (pmu_r32(PWDSR(clk->module)) & clk->bits));
124
125 if (!retry)
126 panic("activating PMU module failed!\n");
127
128 return 0;
129}
130
131/* disable a clock gate */
132static void pmu_disable(struct clk *clk)
133{
134 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
135 PWDCR(clk->module));
136}
137
138/* the pci enable helper */
139static int pci_enable(struct clk *clk)
140{
141 unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
142 /* set bus clock speed */
143 if (of_machine_is_compatible("lantiq,ar9")) {
144 ifccr &= ~0x1f00000;
145 if (clk->rate == CLOCK_33M)
146 ifccr |= 0xe00000;
147 else
148 ifccr |= 0x700000; /* 62.5M */
149 } else {
150 ifccr &= ~0xf00000;
151 if (clk->rate == CLOCK_33M)
152 ifccr |= 0x800000;
153 else
154 ifccr |= 0x400000; /* 62.5M */
155 }
156 ltq_cgu_w32(ifccr, CGU_IFCCR);
157 pmu_enable(clk);
158 return 0;
159}
160
161/* enable the external clock as a source */
162static int pci_ext_enable(struct clk *clk)
163{
164 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16),
165 CGU_IFCCR);
166 ltq_cgu_w32((1 << 30), CGU_PCICR);
167 return 0;
168}
169
170/* disable the external clock as a source */
171static void pci_ext_disable(struct clk *clk)
172{
173 ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16),
174 CGU_IFCCR);
175 ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR);
176}
177
178/* enable a clockout source */
179static int clkout_enable(struct clk *clk)
180{
181 int i;
182
183 /* get the correct rate */
184 for (i = 0; i < 4; i++) {
185 if (clk->rates[i] == clk->rate) {
186 int shift = 14 - (2 * clk->module);
187 unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR);
188
189 ifccr &= ~(3 << shift);
190 ifccr |= i << shift;
191 ltq_cgu_w32(ifccr, CGU_IFCCR);
192 return 0;
193 }
194 }
195 return -1;
196}
197
198/* manage the clock gates via PMU */
199static void clkdev_add_pmu(const char *dev, const char *con,
200 unsigned int module, unsigned int bits)
201{
202 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
203
204 clk->cl.dev_id = dev;
205 clk->cl.con_id = con;
206 clk->cl.clk = clk;
207 clk->enable = pmu_enable;
208 clk->disable = pmu_disable;
209 clk->module = module;
210 clk->bits = bits;
211 clkdev_add(&clk->cl);
212}
213
214/* manage the clock generator */
215static void clkdev_add_cgu(const char *dev, const char *con,
216 unsigned int bits)
217{
218 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
219
220 clk->cl.dev_id = dev;
221 clk->cl.con_id = con;
222 clk->cl.clk = clk;
223 clk->enable = cgu_enable;
224 clk->disable = cgu_disable;
225 clk->bits = bits;
226 clkdev_add(&clk->cl);
227}
228
229/* pci needs its own enable function as the setup is a bit more complex */
230static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
231
232static void clkdev_add_pci(void)
233{
234 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
235 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
236
237 /* main pci clock */
238 clk->cl.dev_id = "17000000.pci";
239 clk->cl.con_id = NULL;
240 clk->cl.clk = clk;
241 clk->rate = CLOCK_33M;
242 clk->rates = valid_pci_rates;
243 clk->enable = pci_enable;
244 clk->disable = pmu_disable;
245 clk->module = 0;
246 clk->bits = PMU_PCI;
247 clkdev_add(&clk->cl);
248
249 /* use internal/external bus clock */
250 clk_ext->cl.dev_id = "17000000.pci";
251 clk_ext->cl.con_id = "external";
252 clk_ext->cl.clk = clk_ext;
253 clk_ext->enable = pci_ext_enable;
254 clk_ext->disable = pci_ext_disable;
255 clkdev_add(&clk_ext->cl);
256}
257
258/* xway socs can generate clocks on gpio pins */
259static unsigned long valid_clkout_rates[4][5] = {
260 {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
261 {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
262 {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
263 {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
264};
265
266static void clkdev_add_clkout(void)
267{
268 int i;
269
270 for (i = 0; i < 4; i++) {
271 struct clk *clk;
272 char *name;
273
274 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
275 sprintf(name, "clkout%d", i);
276
277 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
278 clk->cl.dev_id = "1f103000.cgu";
279 clk->cl.con_id = name;
280 clk->cl.clk = clk;
281 clk->rate = 0;
282 clk->rates = valid_clkout_rates[i];
283 clk->enable = clkout_enable;
284 clk->module = i;
285 clkdev_add(&clk->cl);
286 }
287}
288
289/* bring up all register ranges that we need for basic system control */
290void __init ltq_soc_init(void)
291{
292 struct resource res_pmu, res_cgu, res_ebu;
293 struct device_node *np_pmu =
294 of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
295 struct device_node *np_cgu =
296 of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
297 struct device_node *np_ebu =
298 of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
299
300 /* check if all the core register ranges are available */
301 if (!np_pmu || !np_cgu || !np_ebu)
302 panic("Failed to load core nodess from devicetree");
303
304 if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
305 of_address_to_resource(np_cgu, 0, &res_cgu) ||
306 of_address_to_resource(np_ebu, 0, &res_ebu))
307 panic("Failed to get core resources");
308
309 if ((request_mem_region(res_pmu.start, resource_size(&res_pmu),
310 res_pmu.name) < 0) ||
311 (request_mem_region(res_cgu.start, resource_size(&res_cgu),
312 res_cgu.name) < 0) ||
313 (request_mem_region(res_ebu.start, resource_size(&res_ebu),
314 res_ebu.name) < 0))
315 pr_err("Failed to request core reources");
316
317 pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
318 ltq_cgu_membase = ioremap_nocache(res_cgu.start,
319 resource_size(&res_cgu));
320 ltq_ebu_membase = ioremap_nocache(res_ebu.start,
321 resource_size(&res_ebu));
322 if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
323 panic("Failed to remap core resources");
324
325 /* make sure to unprotect the memory region where flash is located */
326 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
327
328 /* add our generic xway clocks */
329 clkdev_add_pmu("10000000.fpi", NULL, 0, PMU_FPI);
330 clkdev_add_pmu("1e100400.serial", NULL, 0, PMU_ASC0);
331 clkdev_add_pmu("1e100a00.gptu", NULL, 0, PMU_GPT);
332 clkdev_add_pmu("1e100bb0.stp", NULL, 0, PMU_STP);
333 clkdev_add_pmu("1e104100.dma", NULL, 0, PMU_DMA);
334 clkdev_add_pmu("1e100800.spi", NULL, 0, PMU_SPI);
335 clkdev_add_pmu("1e105300.ebu", NULL, 0, PMU_EBU);
336 clkdev_add_clkout();
337
338 /* add the soc dependent clocks */
339 if (!of_machine_is_compatible("lantiq,vr9"))
340 clkdev_add_pmu("1e180000.etop", NULL, 0, PMU_PPE);
341
342 if (!of_machine_is_compatible("lantiq,ase")) {
343 clkdev_add_pmu("1e100c00.serial", NULL, 0, PMU_ASC1);
344 clkdev_add_pci();
345 }
346
347 if (of_machine_is_compatible("lantiq,ase")) {
348 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
349 clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
350 else
351 clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
352 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
353 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
354 } else if (of_machine_is_compatible("lantiq,vr9")) {
355 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
356 ltq_vr9_fpi_hz());
357 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
358 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
359 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
360 clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
361 clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
362 clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
363 } else if (of_machine_is_compatible("lantiq,ar9")) {
364 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
365 ltq_ar9_fpi_hz());
366 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
367 } else {
368 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
369 ltq_danube_fpi_hz());
370 }
371}
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 17:01:42 -0500