MIPS: lantiq: adds static clock for PP32

The Lantiq DSL SoCs have an internal networking processor. Add code to read
the static clock rate.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4815/

2 files changed, 50 insertions, 5 deletions

diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c
index 9aa17f79a742..1ab576dc9bd1 100644
--- a/arch/mips/lantiq/xway/clk.c
+++ b/arch/mips/lantiq/xway/clk.c
@@ -53,6 +53,29 @@ unsigned long ltq_danube_cpu_hz(void)
         }
 }
 
+unsigned long ltq_danube_pp32_hz(void)
+{
+        unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 7) & 3;
+        unsigned long clk;
+
+        switch (clksys) {
+        case 1:
+                clk = CLOCK_240M;
+                break;
+        case 2:
+                clk = CLOCK_222M;
+                break;
+        case 3:
+                clk = CLOCK_133M;
+                break;
+        default:
+                clk = CLOCK_266M;
+                break;
+        }
+
+        return clk;
+}
+
 unsigned long ltq_ar9_sys_hz(void)
 {
         if (((ltq_cgu_r32(CGU_SYS) >> 3) & 0x3) == 0x2)
@@ -149,3 +172,23 @@ unsigned long ltq_vr9_fpi_hz(void)
 
         return clk;
 }
+
+unsigned long ltq_vr9_pp32_hz(void)
+{
+        unsigned int clksys = (ltq_cgu_r32(CGU_SYS) >> 16) & 3;
+        unsigned long clk;
+
+        switch (clksys) {
+        case 1:
+                clk = CLOCK_450M;
+                break;
+        case 2:
+                clk = CLOCK_300M;
+                break;
+        default:
+                clk = CLOCK_500M;
+                break;
+        }
+
+        return clk;
+}
diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
index 1aaa726aad47..3390fcd6ee56 100644
--- a/arch/mips/lantiq/xway/sysctrl.c
+++ b/arch/mips/lantiq/xway/sysctrl.c
@@ -356,14 +356,16 @@ void __init ltq_soc_init(void)
 
         if (of_machine_is_compatible("lantiq,ase")) {
                 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
-                        clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M);
+                        clkdev_add_static(CLOCK_266M, CLOCK_133M,
+                                                CLOCK_133M, CLOCK_266M);
                 else
-                        clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M);
+                        clkdev_add_static(CLOCK_133M, CLOCK_133M,
+                                                CLOCK_133M, CLOCK_133M);
                 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY),
                 clkdev_add_pmu("1e180000.etop", "ephy", 0, PMU_EPHY);
         } else if (of_machine_is_compatible("lantiq,vr9")) {
                 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
-                                ltq_vr9_fpi_hz());
+                                ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
                 clkdev_add_pmu("1d900000.pcie", "phy", 1, PMU1_PCIE_PHY);
                 clkdev_add_pmu("1d900000.pcie", "bus", 0, PMU_PCIE_CLK);
                 clkdev_add_pmu("1d900000.pcie", "msi", 1, PMU1_PCIE_MSI);
@@ -376,10 +378,10 @@ void __init ltq_soc_init(void)
                                 PMU_PPE_QSB | PMU_PPE_TOP);
         } else if (of_machine_is_compatible("lantiq,ar9")) {
                 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
-                                ltq_ar9_fpi_hz());
+                                ltq_ar9_fpi_hz(), CLOCK_250M);
                 clkdev_add_pmu("1e180000.etop", "switch", 0, PMU_SWITCH);
         } else {
                 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
-                                ltq_danube_fpi_hz());
+                                ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
         }
 }