diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 12:17:33 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 12:17:33 -0400 |
commit | ade63aada79c61bcd5f51cbd310f237399892268 (patch) | |
tree | 4f8605528bfd9b6261679883974b9ac4870223dd /arch/mips/kernel | |
parent | 9a1724c7506bfa7d3d9dcab13f83e9e6446929f9 (diff) | |
parent | c14af233fbe279d0e561ecf84f1208b1bae087ef (diff) |
Merge branch '3.14-fixes' into mips-for-linux-next
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/ftrace.c | 5 | ||||
-rw-r--r-- | arch/mips/kernel/r4k_fpu.S | 16 | ||||
-rw-r--r-- | arch/mips/kernel/rtlx-cmp.c | 3 | ||||
-rw-r--r-- | arch/mips/kernel/rtlx-mt.c | 3 |
4 files changed, 16 insertions, 11 deletions
diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c index ddcc3500248d..74fe73506d8f 100644 --- a/arch/mips/kernel/ftrace.c +++ b/arch/mips/kernel/ftrace.c | |||
@@ -115,11 +115,10 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1, | |||
115 | safe_store_code(new_code1, ip, faulted); | 115 | safe_store_code(new_code1, ip, faulted); |
116 | if (unlikely(faulted)) | 116 | if (unlikely(faulted)) |
117 | return -EFAULT; | 117 | return -EFAULT; |
118 | ip += 4; | 118 | safe_store_code(new_code2, ip + 4, faulted); |
119 | safe_store_code(new_code2, ip, faulted); | ||
120 | if (unlikely(faulted)) | 119 | if (unlikely(faulted)) |
121 | return -EFAULT; | 120 | return -EFAULT; |
122 | flush_icache_range(ip, ip + 8); /* original ip + 12 */ | 121 | flush_icache_range(ip, ip + 8); |
123 | return 0; | 122 | return 0; |
124 | } | 123 | } |
125 | #endif | 124 | #endif |
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 0cfa7a56a153..71814272d148 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S | |||
@@ -36,9 +36,9 @@ | |||
36 | LEAF(_save_fp_context) | 36 | LEAF(_save_fp_context) |
37 | cfc1 t1, fcr31 | 37 | cfc1 t1, fcr31 |
38 | 38 | ||
39 | #if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) | 39 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) |
40 | .set push | 40 | .set push |
41 | #ifdef CONFIG_MIPS32_R2 | 41 | #ifdef CONFIG_CPU_MIPS32_R2 |
42 | .set mips64r2 | 42 | .set mips64r2 |
43 | mfc0 t0, CP0_STATUS | 43 | mfc0 t0, CP0_STATUS |
44 | sll t0, t0, 5 | 44 | sll t0, t0, 5 |
@@ -147,11 +147,11 @@ LEAF(_save_fp_context32) | |||
147 | * - cp1 status/control register | 147 | * - cp1 status/control register |
148 | */ | 148 | */ |
149 | LEAF(_restore_fp_context) | 149 | LEAF(_restore_fp_context) |
150 | EX lw t0, SC_FPC_CSR(a0) | 150 | EX lw t1, SC_FPC_CSR(a0) |
151 | 151 | ||
152 | #if defined(CONFIG_64BIT) || defined(CONFIG_MIPS32_R2) | 152 | #if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) |
153 | .set push | 153 | .set push |
154 | #ifdef CONFIG_MIPS32_R2 | 154 | #ifdef CONFIG_CPU_MIPS32_R2 |
155 | .set mips64r2 | 155 | .set mips64r2 |
156 | mfc0 t0, CP0_STATUS | 156 | mfc0 t0, CP0_STATUS |
157 | sll t0, t0, 5 | 157 | sll t0, t0, 5 |
@@ -192,7 +192,7 @@ LEAF(_restore_fp_context) | |||
192 | EX ldc1 $f26, SC_FPREGS+208(a0) | 192 | EX ldc1 $f26, SC_FPREGS+208(a0) |
193 | EX ldc1 $f28, SC_FPREGS+224(a0) | 193 | EX ldc1 $f28, SC_FPREGS+224(a0) |
194 | EX ldc1 $f30, SC_FPREGS+240(a0) | 194 | EX ldc1 $f30, SC_FPREGS+240(a0) |
195 | ctc1 t0, fcr31 | 195 | ctc1 t1, fcr31 |
196 | jr ra | 196 | jr ra |
197 | li v0, 0 # success | 197 | li v0, 0 # success |
198 | END(_restore_fp_context) | 198 | END(_restore_fp_context) |
@@ -200,7 +200,7 @@ LEAF(_restore_fp_context) | |||
200 | #ifdef CONFIG_MIPS32_COMPAT | 200 | #ifdef CONFIG_MIPS32_COMPAT |
201 | LEAF(_restore_fp_context32) | 201 | LEAF(_restore_fp_context32) |
202 | /* Restore an o32 sigcontext. */ | 202 | /* Restore an o32 sigcontext. */ |
203 | EX lw t0, SC32_FPC_CSR(a0) | 203 | EX lw t1, SC32_FPC_CSR(a0) |
204 | 204 | ||
205 | mfc0 t0, CP0_STATUS | 205 | mfc0 t0, CP0_STATUS |
206 | sll t0, t0, 5 | 206 | sll t0, t0, 5 |
@@ -240,7 +240,7 @@ LEAF(_restore_fp_context32) | |||
240 | EX ldc1 $f26, SC32_FPREGS+208(a0) | 240 | EX ldc1 $f26, SC32_FPREGS+208(a0) |
241 | EX ldc1 $f28, SC32_FPREGS+224(a0) | 241 | EX ldc1 $f28, SC32_FPREGS+224(a0) |
242 | EX ldc1 $f30, SC32_FPREGS+240(a0) | 242 | EX ldc1 $f30, SC32_FPREGS+240(a0) |
243 | ctc1 t0, fcr31 | 243 | ctc1 t1, fcr31 |
244 | jr ra | 244 | jr ra |
245 | li v0, 0 # success | 245 | li v0, 0 # success |
246 | END(_restore_fp_context32) | 246 | END(_restore_fp_context32) |
diff --git a/arch/mips/kernel/rtlx-cmp.c b/arch/mips/kernel/rtlx-cmp.c index 56dc69635153..758fb3cd2326 100644 --- a/arch/mips/kernel/rtlx-cmp.c +++ b/arch/mips/kernel/rtlx-cmp.c | |||
@@ -112,5 +112,8 @@ void __exit rtlx_module_exit(void) | |||
112 | 112 | ||
113 | for (i = 0; i < RTLX_CHANNELS; i++) | 113 | for (i = 0; i < RTLX_CHANNELS; i++) |
114 | device_destroy(mt_class, MKDEV(major, i)); | 114 | device_destroy(mt_class, MKDEV(major, i)); |
115 | |||
115 | unregister_chrdev(major, RTLX_MODULE_NAME); | 116 | unregister_chrdev(major, RTLX_MODULE_NAME); |
117 | |||
118 | aprp_hook = NULL; | ||
116 | } | 119 | } |
diff --git a/arch/mips/kernel/rtlx-mt.c b/arch/mips/kernel/rtlx-mt.c index 91d61ba422b4..9c1aca00fd54 100644 --- a/arch/mips/kernel/rtlx-mt.c +++ b/arch/mips/kernel/rtlx-mt.c | |||
@@ -144,5 +144,8 @@ void __exit rtlx_module_exit(void) | |||
144 | 144 | ||
145 | for (i = 0; i < RTLX_CHANNELS; i++) | 145 | for (i = 0; i < RTLX_CHANNELS; i++) |
146 | device_destroy(mt_class, MKDEV(major, i)); | 146 | device_destroy(mt_class, MKDEV(major, i)); |
147 | |||
147 | unregister_chrdev(major, RTLX_MODULE_NAME); | 148 | unregister_chrdev(major, RTLX_MODULE_NAME); |
149 | |||
150 | aprp_hook = NULL; | ||
148 | } | 151 | } |