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authorJayachandran C <jchandra@broadcom.com>2013-06-10 02:30:00 -0400
committerRalf Baechle <ralf@linux-mips.org>2013-06-13 11:46:41 -0400
commit2c952e06e4f57716109b609956eda28c900faac0 (patch)
tree39dc9361773009cdcfdc1e0e1752b446259d7cef /arch/mips/kernel
parent79f8511c83f13689913f54d2f189297c226ec064 (diff)
MIPS: Move cop2 save/restore to switch_to()
Move the common code for saving and restoring platform specific COP2 registers to switch_to(). This will make supporting new platforms (like Netlogic XLP) easier. The platform specific COP2 definitions are to be specified in asm/processor.h and in asm/cop2.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: ddaney.cavm@gmail.com Patchwork: https://patchwork.linux-mips.org/patch/5411/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/octeon_switch.S27
1 files changed, 0 insertions, 27 deletions
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 0e23343eb0a9..22e2aa1e8d37 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -40,33 +40,6 @@
40 cpu_save_nonscratch a0 40 cpu_save_nonscratch a0
41 LONG_S ra, THREAD_REG31(a0) 41 LONG_S ra, THREAD_REG31(a0)
42 42
43 /* check if we need to save COP2 registers */
44 PTR_L t2, TASK_THREAD_INFO(a0)
45 LONG_L t0, ST_OFF(t2)
46 bbit0 t0, 30, 1f
47
48 /* Disable COP2 in the stored process state */
49 li t1, ST0_CU2
50 xor t0, t1
51 LONG_S t0, ST_OFF(t2)
52
53 /* Enable COP2 so we can save it */
54 mfc0 t0, CP0_STATUS
55 or t0, t1
56 mtc0 t0, CP0_STATUS
57
58 /* Save COP2 */
59 daddu a0, THREAD_CP2
60 jal octeon_cop2_save
61 dsubu a0, THREAD_CP2
62
63 /* Disable COP2 now that we are done */
64 mfc0 t0, CP0_STATUS
65 li t1, ST0_CU2
66 xor t0, t1
67 mtc0 t0, CP0_STATUS
68
691:
70#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 43#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
71 /* Check if we need to store CVMSEG state */ 44 /* Check if we need to store CVMSEG state */
72 mfc0 t0, $11,7 /* CvmMemCtl */ 45 mfc0 t0, $11,7 /* CvmMemCtl */