MIPS: Move cache setup to setup_arch().

commit 97ce2c88f9ad42e3c60a9beb9fca87abf3639faa (jump-label: initialize
jump-label subsystem much earlier) breaks MIPS.  The jump_label_init()
call was moved before trap_init() which is where we initialize
flush_icache_range().

In order to be good citizens, we move cache initialization earlier so
that we don't jump through a null flush_icache_range function pointer
when doing the jump label initialization.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3822/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 8 insertions, 5 deletions

diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index c504b212f8f3..a53f8ec37aac 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -605,6 +605,8 @@ void __init setup_arch(char **cmdline_p)
 
         resource_init();
         plat_smp_setup();
+
+        cpu_cache_init();
 }
 
 unsigned long kernelsp[NR_CPUS];
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index ba9376bf52a1..dc019a1f128d 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -106,7 +106,7 @@ asmlinkage __cpuinit void start_secondary(void)
 #endif /* CONFIG_MIPS_MT_SMTC */
         cpu_probe();
         cpu_report();
-        per_cpu_trap_init();
+        per_cpu_trap_init(false);
         mips_clockevent_init();
         mp_ops->init_secondary();
 
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 24325780f831..8e3488afbcc1 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1490,7 +1490,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
         return set_vi_srs_handler(n, addr, 0);
 }
 
-extern void cpu_cache_init(void);
 extern void tlb_init(void);
 extern void flush_tlb_handlers(void);
 
@@ -1517,7 +1516,7 @@ static int __init ulri_disable(char *s)
 }
 __setup("noulri", ulri_disable);
 
-void __cpuinit per_cpu_trap_init(void)
+void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
 {
         unsigned int cpu = smp_processor_id();
         unsigned int status_set = ST0_CU0;
@@ -1616,7 +1615,9 @@ void __cpuinit per_cpu_trap_init(void)
 #ifdef CONFIG_MIPS_MT_SMTC
         if (bootTC) {
 #endif /* CONFIG_MIPS_MT_SMTC */
-                cpu_cache_init();
+                /* Boot CPU's cache setup in setup_arch(). */
+                if (!is_boot_cpu)
+                        cpu_cache_init();
                 tlb_init();
 #ifdef CONFIG_MIPS_MT_SMTC
         } else if (!secondaryTC) {
@@ -1693,7 +1694,7 @@ void __init trap_init(void)
 
         if (board_ebase_setup)
                 board_ebase_setup();
-        per_cpu_trap_init();
+        per_cpu_trap_init(true);
 
         /*
          * Copy the generic exception handlers to their final destination.