Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next

3 files changed, 121 insertions, 50 deletions

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 51095dd9599d..75323925e537 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,7 @@
 #include <asm/smtc_ipi.h>
 #include <asm/time.h>
 #include <asm/cevt-r4k.h>
+#include <asm/gic.h>
 
 /*
  * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
@@ -98,6 +99,10 @@ void mips_event_handler(struct clock_event_device *dev)
  */
 static int c0_compare_int_pending(void)
 {
+#ifdef CONFIG_IRQ_GIC
+        if (cpu_has_veic)
+                return gic_get_timer_pending();
+#endif
         return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
 }
 
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 0beb75fb3980..bc58bd10a607 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -861,6 +861,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_1004K;
                 __cpu_name[cpu] = "MIPS 1004Kc";
                 break;
+        case PRID_IMP_1074K:
+                c->cputype = CPU_74K;
+                __cpu_name[cpu] = "MIPS 1074Kc";
+                break;
         }
 
         spram_config();
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 0c527f652196..485e6a961b31 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -1,5 +1,11 @@
-#undef DEBUG
-
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
+ * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
+ */
 #include <linux/bitmap.h>
 #include <linux/init.h>
 #include <linux/smp.h>
@@ -7,33 +13,80 @@
 
 #include <asm/io.h>
 #include <asm/gic.h>
+#include <asm/setup.h>
+#include <asm/traps.h>
 #include <asm/gcmpregs.h>
 #include <linux/hardirq.h>
 #include <asm-generic/bitops/find.h>
 
+unsigned long _gic_base;
+unsigned int gic_irq_base;
+unsigned int gic_irq_flags[GIC_NUM_INTRS];
 
-static unsigned long _gic_base;
-static unsigned int _irqbase;
-static unsigned int gic_irq_flags[GIC_NUM_INTRS];
-#define GIC_IRQ_FLAG_EDGE      0x0001
+/* The index into this array is the vector # of the interrupt. */
+struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
 
-struct gic_pcpu_mask pcpu_masks[NR_CPUS];
+static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
 static struct gic_pending_regs pending_regs[NR_CPUS];
 static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
 
+unsigned int gic_get_timer_pending(void)
+{
+        unsigned int vpe_pending;
+
+        GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
+        GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
+        return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
+}
+
+void gic_bind_eic_interrupt(int irq, int set)
+{
+        /* Convert irq vector # to hw int # */
+        irq -= GIC_PIN_TO_VEC_OFFSET;
+
+        /* Set irq to use shadow set */
+        GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
+}
+
 void gic_send_ipi(unsigned int intr)
 {
-        pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__,
-                 read_c0_status());
         GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
 }
 
-/* This is Malta specific and needs to be exported */
+static void gic_eic_irq_dispatch(void)
+{
+        unsigned int cause = read_c0_cause();
+        int irq;
+
+        irq = (cause & ST0_IM) >> STATUSB_IP2;
+        if (irq == 0)
+                irq = -1;
+
+        if (irq >= 0)
+                do_IRQ(gic_irq_base + irq);
+        else
+                spurious_interrupt();
+}
+
 static void __init vpe_local_setup(unsigned int numvpes)
 {
-        int i;
-        unsigned long timer_interrupt = 5, perf_interrupt = 5;
+        unsigned long timer_intr = GIC_INT_TMR;
+        unsigned long perf_intr = GIC_INT_PERFCTR;
         unsigned int vpe_ctl;
+        int i;
+
+        if (cpu_has_veic) {
+                /*
+                 * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
+                 * map to pin X+2-1 (since GIC adds 1)
+                 */
+                timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+                /*
+                 * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
+                 * map to pin X+2-1 (since GIC adds 1)
+                 */
+                perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+        }
 
         /*
          * Setup the default performance counter timer interrupts
@@ -46,11 +99,20 @@ static void __init vpe_local_setup(unsigned int numvpes)
                 GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
                 if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
-                                 GIC_MAP_TO_PIN_MSK | timer_interrupt);
+                                 GIC_MAP_TO_PIN_MSK | timer_intr);
+                if (cpu_has_veic) {
+                        set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
+                                gic_eic_irq_dispatch);
+                        gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
+                }
 
                 if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
                         GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
-                                 GIC_MAP_TO_PIN_MSK | perf_interrupt);
+                                 GIC_MAP_TO_PIN_MSK | perf_intr);
+                if (cpu_has_veic) {
+                        set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
+                        gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
+                }
         }
 }
 
@@ -80,51 +142,30 @@ unsigned int gic_get_int(void)
         bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
         bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
 
-        i = find_first_bit(pending, GIC_NUM_INTRS);
-
-        pr_debug("CPU%d: %s pend=%d\n", smp_processor_id(), __func__, i);
-
-        return i;
-}
-
-static void gic_irq_ack(struct irq_data *d)
-{
-        unsigned int irq = d->irq - _irqbase;
-
-        pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
-        GIC_CLR_INTR_MASK(irq);
-
-        if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE)
-                GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq);
+        return find_first_bit(pending, GIC_NUM_INTRS);
 }
 
 static void gic_mask_irq(struct irq_data *d)
 {
-        unsigned int irq = d->irq - _irqbase;
-        pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
-        GIC_CLR_INTR_MASK(irq);
+        GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
 }
 
 static void gic_unmask_irq(struct irq_data *d)
 {
-        unsigned int irq = d->irq - _irqbase;
-        pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq);
-        GIC_SET_INTR_MASK(irq);
+        GIC_SET_INTR_MASK(d->irq - gic_irq_base);
 }
 
 #ifdef CONFIG_SMP
-
 static DEFINE_SPINLOCK(gic_lock);
 
 static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
                             bool force)
 {
-        unsigned int irq = d->irq - _irqbase;
+        unsigned int irq = (d->irq - gic_irq_base);
         cpumask_t       tmp = CPU_MASK_NONE;
         unsigned long   flags;
         int             i;
 
-        pr_debug("%s(%d) called\n", __func__, irq);
         cpumask_and(&tmp, cpumask, cpu_online_mask);
         if (cpus_empty(tmp))
                 return -1;
@@ -154,7 +195,7 @@ static struct irq_chip gic_irq_controller = {
         .irq_mask               =       gic_mask_irq,
         .irq_mask_ack           =       gic_mask_irq,
         .irq_unmask             =       gic_unmask_irq,
-        .irq_eoi                =       gic_unmask_irq,
+        .irq_eoi                =       gic_finish_irq,
 #ifdef CONFIG_SMP
         .irq_set_affinity       =       gic_set_affinity,
 #endif
@@ -164,6 +205,8 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
         unsigned int pin, unsigned int polarity, unsigned int trigtype,
         unsigned int flags)
 {
+        struct gic_shared_intr_map *map_ptr;
+
         /* Setup Intr to Pin mapping */
         if (pin & GIC_MAP_TO_NMI_MSK) {
                 GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
@@ -178,6 +221,14 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
                          GIC_MAP_TO_PIN_MSK | pin);
                 /* Setup Intr to CPU mapping */
                 GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
+                if (cpu_has_veic) {
+                        set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
+                                gic_eic_irq_dispatch);
+                        map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
+                        if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
+                                BUG();
+                        map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
+                }
         }
 
         /* Setup Intr Polarity */
@@ -191,26 +242,39 @@ static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
         /* Initialise per-cpu Interrupt software masks */
         if (flags & GIC_FLAG_IPI)
                 set_bit(intr, pcpu_masks[cpu].pcpu_mask);
-        if (flags & GIC_FLAG_TRANSPARENT)
+        if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
                 GIC_SET_INTR_MASK(intr);
         if (trigtype == GIC_TRIG_EDGE)
-                gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE;
+                gic_irq_flags[intr] |= GIC_TRIG_EDGE;
 }
 
 static void __init gic_basic_init(int numintrs, int numvpes,
                         struct gic_intr_map *intrmap, int mapsize)
 {
         unsigned int i, cpu;
+        unsigned int pin_offset = 0;
+
+        board_bind_eic_interrupt = &gic_bind_eic_interrupt;
 
         /* Setup defaults */
         for (i = 0; i < numintrs; i++) {
                 GIC_SET_POLARITY(i, GIC_POL_POS);
                 GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
                 GIC_CLR_INTR_MASK(i);
-                if (i < GIC_NUM_INTRS)
+                if (i < GIC_NUM_INTRS) {
                         gic_irq_flags[i] = 0;
+                        gic_shared_intr_map[i].num_shared_intr = 0;
+                        gic_shared_intr_map[i].local_intr_mask = 0;
+                }
         }
 
+        /*
+         * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
+         * one because the GIC will add one (since 0=no intr).
+         */
+        if (cpu_has_veic)
+                pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
+
         /* Setup specifics */
         for (i = 0; i < mapsize; i++) {
                 cpu = intrmap[i].cpunum;
@@ -220,16 +284,13 @@ static void __init gic_basic_init(int numintrs, int numvpes,
                         continue;
                 gic_setup_intr(i,
                         intrmap[i].cpunum,
-                        intrmap[i].pin,
+                        intrmap[i].pin + pin_offset,
                         intrmap[i].polarity,
                         intrmap[i].trigtype,
                         intrmap[i].flags);
         }
 
         vpe_local_setup(numvpes);
-
-        for (i = _irqbase; i < (_irqbase + numintrs); i++)
-                irq_set_chip(i, &gic_irq_controller);
 }
 
 void __init gic_init(unsigned long gic_base_addr,
@@ -242,7 +303,7 @@ void __init gic_init(unsigned long gic_base_addr,
 
         _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
                                                     gic_addrspace_size);
-        _irqbase = irqbase;
+        gic_irq_base = irqbase;
 
         GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
         numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
@@ -251,8 +312,9 @@ void __init gic_init(unsigned long gic_base_addr,
 
         numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
                   GIC_SH_CONFIG_NUMVPES_SHF;
-
-        pr_debug("%s called\n", __func__);
+        numvpes = numvpes + 1;
 
         gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
+
+        gic_platform_init(numintrs, &gic_irq_controller);
 }