diff options
author | Atsushi Nemoto <anemo@mba.ocn.ne.jp> | 2006-11-01 12:08:36 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-11-29 20:14:46 -0500 |
commit | 1603b5aca4f15b34848fb5594d0c7b6333b99144 (patch) | |
tree | 79272aa41d6510b7256df62e287676885c3960cf /arch/mips/kernel | |
parent | c87b6ebaea034c0e0ce86127870cf1511a307b64 (diff) |
[MIPS] IRQ cleanups
This is a big irq cleanup patch.
* Use set_irq_chip() to register irq_chip.
* Initialize .mask, .unmask, .mask_ack field. Functions for these
method are already exist in most case.
* Do not initialize .startup, .shutdown, .enable, .disable fields if
default routines provided by irq_chip_set_defaults() were suitable.
* Remove redundant irq_desc initializations.
* Remove unnecessary local_irq_save/local_irq_restore, spin_lock.
With this cleanup, it would be easy to switch to slightly lightwait
irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ().
Though whole this patch is quite large, changes in each irq_chip are
not quite simple. Please review and test on your platform. Thanks.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/i8259.c | 21 | ||||
-rw-r--r-- | arch/mips/kernel/irq-msc01.c | 45 | ||||
-rw-r--r-- | arch/mips/kernel/irq-mv6434x.c | 53 | ||||
-rw-r--r-- | arch/mips/kernel/irq-rm7000.c | 53 | ||||
-rw-r--r-- | arch/mips/kernel/irq-rm9000.c | 45 | ||||
-rw-r--r-- | arch/mips/kernel/irq.c | 13 | ||||
-rw-r--r-- | arch/mips/kernel/irq_cpu.c | 77 |
7 files changed, 47 insertions, 260 deletions
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c index 48e3418c217b..2526c0ca4d81 100644 --- a/arch/mips/kernel/i8259.c +++ b/arch/mips/kernel/i8259.c | |||
@@ -40,21 +40,10 @@ static void end_8259A_irq (unsigned int irq) | |||
40 | enable_8259A_irq(irq); | 40 | enable_8259A_irq(irq); |
41 | } | 41 | } |
42 | 42 | ||
43 | #define shutdown_8259A_irq disable_8259A_irq | ||
44 | |||
45 | void mask_and_ack_8259A(unsigned int); | 43 | void mask_and_ack_8259A(unsigned int); |
46 | 44 | ||
47 | static unsigned int startup_8259A_irq(unsigned int irq) | ||
48 | { | ||
49 | enable_8259A_irq(irq); | ||
50 | |||
51 | return 0; /* never anything pending */ | ||
52 | } | ||
53 | |||
54 | static struct irq_chip i8259A_irq_type = { | 45 | static struct irq_chip i8259A_irq_type = { |
55 | .typename = "XT-PIC", | 46 | .typename = "XT-PIC", |
56 | .startup = startup_8259A_irq, | ||
57 | .shutdown = shutdown_8259A_irq, | ||
58 | .enable = enable_8259A_irq, | 47 | .enable = enable_8259A_irq, |
59 | .disable = disable_8259A_irq, | 48 | .disable = disable_8259A_irq, |
60 | .ack = mask_and_ack_8259A, | 49 | .ack = mask_and_ack_8259A, |
@@ -120,7 +109,7 @@ int i8259A_irq_pending(unsigned int irq) | |||
120 | void make_8259A_irq(unsigned int irq) | 109 | void make_8259A_irq(unsigned int irq) |
121 | { | 110 | { |
122 | disable_irq_nosync(irq); | 111 | disable_irq_nosync(irq); |
123 | irq_desc[irq].chip = &i8259A_irq_type; | 112 | set_irq_chip(irq, &i8259A_irq_type); |
124 | enable_irq(irq); | 113 | enable_irq(irq); |
125 | } | 114 | } |
126 | 115 | ||
@@ -323,12 +312,8 @@ void __init init_i8259_irqs (void) | |||
323 | 312 | ||
324 | init_8259A(0); | 313 | init_8259A(0); |
325 | 314 | ||
326 | for (i = 0; i < 16; i++) { | 315 | for (i = 0; i < 16; i++) |
327 | irq_desc[i].status = IRQ_DISABLED; | 316 | set_irq_chip(i, &i8259A_irq_type); |
328 | irq_desc[i].action = NULL; | ||
329 | irq_desc[i].depth = 1; | ||
330 | irq_desc[i].chip = &i8259A_irq_type; | ||
331 | } | ||
332 | 317 | ||
333 | setup_irq(2, &irq2); | 318 | setup_irq(2, &irq2); |
334 | } | 319 | } |
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 650a80ca3741..e1880b27381b 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
@@ -45,31 +45,6 @@ static inline void unmask_msc_irq(unsigned int irq) | |||
45 | } | 45 | } |
46 | 46 | ||
47 | /* | 47 | /* |
48 | * Enables the IRQ on SOC-it | ||
49 | */ | ||
50 | static void enable_msc_irq(unsigned int irq) | ||
51 | { | ||
52 | unmask_msc_irq(irq); | ||
53 | } | ||
54 | |||
55 | /* | ||
56 | * Initialize the IRQ on SOC-it | ||
57 | */ | ||
58 | static unsigned int startup_msc_irq(unsigned int irq) | ||
59 | { | ||
60 | unmask_msc_irq(irq); | ||
61 | return 0; | ||
62 | } | ||
63 | |||
64 | /* | ||
65 | * Disables the IRQ on SOC-it | ||
66 | */ | ||
67 | static void disable_msc_irq(unsigned int irq) | ||
68 | { | ||
69 | mask_msc_irq(irq); | ||
70 | } | ||
71 | |||
72 | /* | ||
73 | * Masks and ACKs an IRQ | 48 | * Masks and ACKs an IRQ |
74 | */ | 49 | */ |
75 | static void level_mask_and_ack_msc_irq(unsigned int irq) | 50 | static void level_mask_and_ack_msc_irq(unsigned int irq) |
@@ -136,25 +111,21 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set) | |||
136 | (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); | 111 | (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); |
137 | } | 112 | } |
138 | 113 | ||
139 | #define shutdown_msc_irq disable_msc_irq | ||
140 | |||
141 | struct irq_chip msc_levelirq_type = { | 114 | struct irq_chip msc_levelirq_type = { |
142 | .typename = "SOC-it-Level", | 115 | .typename = "SOC-it-Level", |
143 | .startup = startup_msc_irq, | ||
144 | .shutdown = shutdown_msc_irq, | ||
145 | .enable = enable_msc_irq, | ||
146 | .disable = disable_msc_irq, | ||
147 | .ack = level_mask_and_ack_msc_irq, | 116 | .ack = level_mask_and_ack_msc_irq, |
117 | .mask = mask_msc_irq, | ||
118 | .mask_ack = level_mask_and_ack_msc_irq, | ||
119 | .unmask = unmask_msc_irq, | ||
148 | .end = end_msc_irq, | 120 | .end = end_msc_irq, |
149 | }; | 121 | }; |
150 | 122 | ||
151 | struct irq_chip msc_edgeirq_type = { | 123 | struct irq_chip msc_edgeirq_type = { |
152 | .typename = "SOC-it-Edge", | 124 | .typename = "SOC-it-Edge", |
153 | .startup =startup_msc_irq, | ||
154 | .shutdown = shutdown_msc_irq, | ||
155 | .enable = enable_msc_irq, | ||
156 | .disable = disable_msc_irq, | ||
157 | .ack = edge_mask_and_ack_msc_irq, | 125 | .ack = edge_mask_and_ack_msc_irq, |
126 | .mask = mask_msc_irq, | ||
127 | .mask_ack = edge_mask_and_ack_msc_irq, | ||
128 | .unmask = unmask_msc_irq, | ||
158 | .end = end_msc_irq, | 129 | .end = end_msc_irq, |
159 | }; | 130 | }; |
160 | 131 | ||
@@ -175,14 +146,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq) | |||
175 | 146 | ||
176 | switch (imp->im_type) { | 147 | switch (imp->im_type) { |
177 | case MSC01_IRQ_EDGE: | 148 | case MSC01_IRQ_EDGE: |
178 | irq_desc[base+n].chip = &msc_edgeirq_type; | 149 | set_irq_chip(base+n, &msc_edgeirq_type); |
179 | if (cpu_has_veic) | 150 | if (cpu_has_veic) |
180 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); | 151 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); |
181 | else | 152 | else |
182 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); | 153 | MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); |
183 | break; | 154 | break; |
184 | case MSC01_IRQ_LEVEL: | 155 | case MSC01_IRQ_LEVEL: |
185 | irq_desc[base+n].chip = &msc_levelirq_type; | 156 | set_irq_chip(base+n, &msc_levelirq_type); |
186 | if (cpu_has_veic) | 157 | if (cpu_has_veic) |
187 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); | 158 | MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); |
188 | else | 159 | else |
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c index 37d106202b83..5012b9df1b5a 100644 --- a/arch/mips/kernel/irq-mv6434x.c +++ b/arch/mips/kernel/irq-mv6434x.c | |||
@@ -67,39 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq) | |||
67 | } | 67 | } |
68 | 68 | ||
69 | /* | 69 | /* |
70 | * Enables the IRQ on Marvell Chip | ||
71 | */ | ||
72 | static void enable_mv64340_irq(unsigned int irq) | ||
73 | { | ||
74 | unmask_mv64340_irq(irq); | ||
75 | } | ||
76 | |||
77 | /* | ||
78 | * Initialize the IRQ on Marvell Chip | ||
79 | */ | ||
80 | static unsigned int startup_mv64340_irq(unsigned int irq) | ||
81 | { | ||
82 | unmask_mv64340_irq(irq); | ||
83 | return 0; | ||
84 | } | ||
85 | |||
86 | /* | ||
87 | * Disables the IRQ on Marvell Chip | ||
88 | */ | ||
89 | static void disable_mv64340_irq(unsigned int irq) | ||
90 | { | ||
91 | mask_mv64340_irq(irq); | ||
92 | } | ||
93 | |||
94 | /* | ||
95 | * Masks and ACKs an IRQ | ||
96 | */ | ||
97 | static void mask_and_ack_mv64340_irq(unsigned int irq) | ||
98 | { | ||
99 | mask_mv64340_irq(irq); | ||
100 | } | ||
101 | |||
102 | /* | ||
103 | * End IRQ processing | 70 | * End IRQ processing |
104 | */ | 71 | */ |
105 | static void end_mv64340_irq(unsigned int irq) | 72 | static void end_mv64340_irq(unsigned int irq) |
@@ -133,15 +100,12 @@ void ll_mv64340_irq(void) | |||
133 | do_IRQ(ls1bit32(irq_src_high) + irq_base + 32); | 100 | do_IRQ(ls1bit32(irq_src_high) + irq_base + 32); |
134 | } | 101 | } |
135 | 102 | ||
136 | #define shutdown_mv64340_irq disable_mv64340_irq | ||
137 | |||
138 | struct irq_chip mv64340_irq_type = { | 103 | struct irq_chip mv64340_irq_type = { |
139 | .typename = "MV-64340", | 104 | .typename = "MV-64340", |
140 | .startup = startup_mv64340_irq, | 105 | .ack = mask_mv64340_irq, |
141 | .shutdown = shutdown_mv64340_irq, | 106 | .mask = mask_mv64340_irq, |
142 | .enable = enable_mv64340_irq, | 107 | .mask_ack = mask_mv64340_irq, |
143 | .disable = disable_mv64340_irq, | 108 | .unmask = unmask_mv64340_irq, |
144 | .ack = mask_and_ack_mv64340_irq, | ||
145 | .end = end_mv64340_irq, | 109 | .end = end_mv64340_irq, |
146 | }; | 110 | }; |
147 | 111 | ||
@@ -149,13 +113,8 @@ void __init mv64340_irq_init(unsigned int base) | |||
149 | { | 113 | { |
150 | int i; | 114 | int i; |
151 | 115 | ||
152 | /* Reset irq handlers pointers to NULL */ | 116 | for (i = base; i < base + 64; i++) |
153 | for (i = base; i < base + 64; i++) { | 117 | set_irq_chip(i, &mv64340_irq_type); |
154 | irq_desc[i].status = IRQ_DISABLED; | ||
155 | irq_desc[i].action = 0; | ||
156 | irq_desc[i].depth = 2; | ||
157 | irq_desc[i].chip = &mv64340_irq_type; | ||
158 | } | ||
159 | 118 | ||
160 | irq_base = base; | 119 | irq_base = base; |
161 | } | 120 | } |
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c index 6b54c7109e2e..6a297e3b8899 100644 --- a/arch/mips/kernel/irq-rm7000.c +++ b/arch/mips/kernel/irq-rm7000.c | |||
@@ -29,42 +29,6 @@ static inline void mask_rm7k_irq(unsigned int irq) | |||
29 | clear_c0_intcontrol(0x100 << (irq - irq_base)); | 29 | clear_c0_intcontrol(0x100 << (irq - irq_base)); |
30 | } | 30 | } |
31 | 31 | ||
32 | static inline void rm7k_cpu_irq_enable(unsigned int irq) | ||
33 | { | ||
34 | unsigned long flags; | ||
35 | |||
36 | local_irq_save(flags); | ||
37 | unmask_rm7k_irq(irq); | ||
38 | local_irq_restore(flags); | ||
39 | } | ||
40 | |||
41 | static void rm7k_cpu_irq_disable(unsigned int irq) | ||
42 | { | ||
43 | unsigned long flags; | ||
44 | |||
45 | local_irq_save(flags); | ||
46 | mask_rm7k_irq(irq); | ||
47 | local_irq_restore(flags); | ||
48 | } | ||
49 | |||
50 | static unsigned int rm7k_cpu_irq_startup(unsigned int irq) | ||
51 | { | ||
52 | rm7k_cpu_irq_enable(irq); | ||
53 | |||
54 | return 0; | ||
55 | } | ||
56 | |||
57 | #define rm7k_cpu_irq_shutdown rm7k_cpu_irq_disable | ||
58 | |||
59 | /* | ||
60 | * While we ack the interrupt interrupts are disabled and thus we don't need | ||
61 | * to deal with concurrency issues. Same for rm7k_cpu_irq_end. | ||
62 | */ | ||
63 | static void rm7k_cpu_irq_ack(unsigned int irq) | ||
64 | { | ||
65 | mask_rm7k_irq(irq); | ||
66 | } | ||
67 | |||
68 | static void rm7k_cpu_irq_end(unsigned int irq) | 32 | static void rm7k_cpu_irq_end(unsigned int irq) |
69 | { | 33 | { |
70 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | 34 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
@@ -73,11 +37,10 @@ static void rm7k_cpu_irq_end(unsigned int irq) | |||
73 | 37 | ||
74 | static struct irq_chip rm7k_irq_controller = { | 38 | static struct irq_chip rm7k_irq_controller = { |
75 | .typename = "RM7000", | 39 | .typename = "RM7000", |
76 | .startup = rm7k_cpu_irq_startup, | 40 | .ack = mask_rm7k_irq, |
77 | .shutdown = rm7k_cpu_irq_shutdown, | 41 | .mask = mask_rm7k_irq, |
78 | .enable = rm7k_cpu_irq_enable, | 42 | .mask_ack = mask_rm7k_irq, |
79 | .disable = rm7k_cpu_irq_disable, | 43 | .unmask = unmask_rm7k_irq, |
80 | .ack = rm7k_cpu_irq_ack, | ||
81 | .end = rm7k_cpu_irq_end, | 44 | .end = rm7k_cpu_irq_end, |
82 | }; | 45 | }; |
83 | 46 | ||
@@ -87,12 +50,8 @@ void __init rm7k_cpu_irq_init(int base) | |||
87 | 50 | ||
88 | clear_c0_intcontrol(0x00000f00); /* Mask all */ | 51 | clear_c0_intcontrol(0x00000f00); /* Mask all */ |
89 | 52 | ||
90 | for (i = base; i < base + 4; i++) { | 53 | for (i = base; i < base + 4; i++) |
91 | irq_desc[i].status = IRQ_DISABLED; | 54 | set_irq_chip(i, &rm7k_irq_controller); |
92 | irq_desc[i].action = NULL; | ||
93 | irq_desc[i].depth = 1; | ||
94 | irq_desc[i].chip = &rm7k_irq_controller; | ||
95 | } | ||
96 | 55 | ||
97 | irq_base = base; | 56 | irq_base = base; |
98 | } | 57 | } |
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c index 62f011ba97a2..977538445cf3 100644 --- a/arch/mips/kernel/irq-rm9000.c +++ b/arch/mips/kernel/irq-rm9000.c | |||
@@ -48,15 +48,6 @@ static void rm9k_cpu_irq_disable(unsigned int irq) | |||
48 | local_irq_restore(flags); | 48 | local_irq_restore(flags); |
49 | } | 49 | } |
50 | 50 | ||
51 | static unsigned int rm9k_cpu_irq_startup(unsigned int irq) | ||
52 | { | ||
53 | rm9k_cpu_irq_enable(irq); | ||
54 | |||
55 | return 0; | ||
56 | } | ||
57 | |||
58 | #define rm9k_cpu_irq_shutdown rm9k_cpu_irq_disable | ||
59 | |||
60 | /* | 51 | /* |
61 | * Performance counter interrupts are global on all processors. | 52 | * Performance counter interrupts are global on all processors. |
62 | */ | 53 | */ |
@@ -89,16 +80,6 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq) | |||
89 | on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); | 80 | on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); |
90 | } | 81 | } |
91 | 82 | ||
92 | |||
93 | /* | ||
94 | * While we ack the interrupt interrupts are disabled and thus we don't need | ||
95 | * to deal with concurrency issues. Same for rm9k_cpu_irq_end. | ||
96 | */ | ||
97 | static void rm9k_cpu_irq_ack(unsigned int irq) | ||
98 | { | ||
99 | mask_rm9k_irq(irq); | ||
100 | } | ||
101 | |||
102 | static void rm9k_cpu_irq_end(unsigned int irq) | 83 | static void rm9k_cpu_irq_end(unsigned int irq) |
103 | { | 84 | { |
104 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | 85 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
@@ -107,11 +88,10 @@ static void rm9k_cpu_irq_end(unsigned int irq) | |||
107 | 88 | ||
108 | static struct irq_chip rm9k_irq_controller = { | 89 | static struct irq_chip rm9k_irq_controller = { |
109 | .typename = "RM9000", | 90 | .typename = "RM9000", |
110 | .startup = rm9k_cpu_irq_startup, | 91 | .ack = mask_rm9k_irq, |
111 | .shutdown = rm9k_cpu_irq_shutdown, | 92 | .mask = mask_rm9k_irq, |
112 | .enable = rm9k_cpu_irq_enable, | 93 | .mask_ack = mask_rm9k_irq, |
113 | .disable = rm9k_cpu_irq_disable, | 94 | .unmask = unmask_rm9k_irq, |
114 | .ack = rm9k_cpu_irq_ack, | ||
115 | .end = rm9k_cpu_irq_end, | 95 | .end = rm9k_cpu_irq_end, |
116 | }; | 96 | }; |
117 | 97 | ||
@@ -119,9 +99,10 @@ static struct irq_chip rm9k_perfcounter_irq = { | |||
119 | .typename = "RM9000", | 99 | .typename = "RM9000", |
120 | .startup = rm9k_perfcounter_irq_startup, | 100 | .startup = rm9k_perfcounter_irq_startup, |
121 | .shutdown = rm9k_perfcounter_irq_shutdown, | 101 | .shutdown = rm9k_perfcounter_irq_shutdown, |
122 | .enable = rm9k_cpu_irq_enable, | 102 | .ack = mask_rm9k_irq, |
123 | .disable = rm9k_cpu_irq_disable, | 103 | .mask = mask_rm9k_irq, |
124 | .ack = rm9k_cpu_irq_ack, | 104 | .mask_ack = mask_rm9k_irq, |
105 | .unmask = unmask_rm9k_irq, | ||
125 | .end = rm9k_cpu_irq_end, | 106 | .end = rm9k_cpu_irq_end, |
126 | }; | 107 | }; |
127 | 108 | ||
@@ -135,15 +116,11 @@ void __init rm9k_cpu_irq_init(int base) | |||
135 | 116 | ||
136 | clear_c0_intcontrol(0x0000f000); /* Mask all */ | 117 | clear_c0_intcontrol(0x0000f000); /* Mask all */ |
137 | 118 | ||
138 | for (i = base; i < base + 4; i++) { | 119 | for (i = base; i < base + 4; i++) |
139 | irq_desc[i].status = IRQ_DISABLED; | 120 | set_irq_chip(i, &rm9k_irq_controller); |
140 | irq_desc[i].action = NULL; | ||
141 | irq_desc[i].depth = 1; | ||
142 | irq_desc[i].chip = &rm9k_irq_controller; | ||
143 | } | ||
144 | 121 | ||
145 | rm9000_perfcount_irq = base + 1; | 122 | rm9000_perfcount_irq = base + 1; |
146 | irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; | 123 | set_irq_chip(rm9000_perfcount_irq, &rm9k_perfcounter_irq); |
147 | 124 | ||
148 | irq_base = base; | 125 | irq_base = base; |
149 | } | 126 | } |
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index 9b0e49d63d7b..e997c9454f47 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c | |||
@@ -172,19 +172,6 @@ __setup("nokgdb", nokgdb); | |||
172 | 172 | ||
173 | void __init init_IRQ(void) | 173 | void __init init_IRQ(void) |
174 | { | 174 | { |
175 | int i; | ||
176 | |||
177 | for (i = 0; i < NR_IRQS; i++) { | ||
178 | irq_desc[i].status = IRQ_DISABLED; | ||
179 | irq_desc[i].action = NULL; | ||
180 | irq_desc[i].depth = 1; | ||
181 | irq_desc[i].chip = &no_irq_chip; | ||
182 | spin_lock_init(&irq_desc[i].lock); | ||
183 | #ifdef CONFIG_MIPS_MT_SMTC | ||
184 | irq_hwmask[i] = 0; | ||
185 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
186 | } | ||
187 | |||
188 | arch_init_irq(); | 175 | arch_init_irq(); |
189 | 176 | ||
190 | #ifdef CONFIG_KGDB | 177 | #ifdef CONFIG_KGDB |
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c index 9bb21c7f2149..3b7cfa407e87 100644 --- a/arch/mips/kernel/irq_cpu.c +++ b/arch/mips/kernel/irq_cpu.c | |||
@@ -50,44 +50,6 @@ static inline void mask_mips_irq(unsigned int irq) | |||
50 | irq_disable_hazard(); | 50 | irq_disable_hazard(); |
51 | } | 51 | } |
52 | 52 | ||
53 | static inline void mips_cpu_irq_enable(unsigned int irq) | ||
54 | { | ||
55 | unsigned long flags; | ||
56 | |||
57 | local_irq_save(flags); | ||
58 | unmask_mips_irq(irq); | ||
59 | back_to_back_c0_hazard(); | ||
60 | local_irq_restore(flags); | ||
61 | } | ||
62 | |||
63 | static void mips_cpu_irq_disable(unsigned int irq) | ||
64 | { | ||
65 | unsigned long flags; | ||
66 | |||
67 | local_irq_save(flags); | ||
68 | mask_mips_irq(irq); | ||
69 | back_to_back_c0_hazard(); | ||
70 | local_irq_restore(flags); | ||
71 | } | ||
72 | |||
73 | static unsigned int mips_cpu_irq_startup(unsigned int irq) | ||
74 | { | ||
75 | mips_cpu_irq_enable(irq); | ||
76 | |||
77 | return 0; | ||
78 | } | ||
79 | |||
80 | #define mips_cpu_irq_shutdown mips_cpu_irq_disable | ||
81 | |||
82 | /* | ||
83 | * While we ack the interrupt interrupts are disabled and thus we don't need | ||
84 | * to deal with concurrency issues. Same for mips_cpu_irq_end. | ||
85 | */ | ||
86 | static void mips_cpu_irq_ack(unsigned int irq) | ||
87 | { | ||
88 | mask_mips_irq(irq); | ||
89 | } | ||
90 | |||
91 | static void mips_cpu_irq_end(unsigned int irq) | 53 | static void mips_cpu_irq_end(unsigned int irq) |
92 | { | 54 | { |
93 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) | 55 | if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) |
@@ -96,11 +58,10 @@ static void mips_cpu_irq_end(unsigned int irq) | |||
96 | 58 | ||
97 | static struct irq_chip mips_cpu_irq_controller = { | 59 | static struct irq_chip mips_cpu_irq_controller = { |
98 | .typename = "MIPS", | 60 | .typename = "MIPS", |
99 | .startup = mips_cpu_irq_startup, | 61 | .ack = mask_mips_irq, |
100 | .shutdown = mips_cpu_irq_shutdown, | 62 | .mask = mask_mips_irq, |
101 | .enable = mips_cpu_irq_enable, | 63 | .mask_ack = mask_mips_irq, |
102 | .disable = mips_cpu_irq_disable, | 64 | .unmask = unmask_mips_irq, |
103 | .ack = mips_cpu_irq_ack, | ||
104 | .end = mips_cpu_irq_end, | 65 | .end = mips_cpu_irq_end, |
105 | }; | 66 | }; |
106 | 67 | ||
@@ -110,8 +71,6 @@ static struct irq_chip mips_cpu_irq_controller = { | |||
110 | 71 | ||
111 | #define unmask_mips_mt_irq unmask_mips_irq | 72 | #define unmask_mips_mt_irq unmask_mips_irq |
112 | #define mask_mips_mt_irq mask_mips_irq | 73 | #define mask_mips_mt_irq mask_mips_irq |
113 | #define mips_mt_cpu_irq_enable mips_cpu_irq_enable | ||
114 | #define mips_mt_cpu_irq_disable mips_cpu_irq_disable | ||
115 | 74 | ||
116 | static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) | 75 | static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) |
117 | { | 76 | { |
@@ -119,13 +78,11 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) | |||
119 | 78 | ||
120 | clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); | 79 | clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); |
121 | evpe(vpflags); | 80 | evpe(vpflags); |
122 | mips_mt_cpu_irq_enable(irq); | 81 | unmask_mips_mt_irq(irq); |
123 | 82 | ||
124 | return 0; | 83 | return 0; |
125 | } | 84 | } |
126 | 85 | ||
127 | #define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable | ||
128 | |||
129 | /* | 86 | /* |
130 | * While we ack the interrupt interrupts are disabled and thus we don't need | 87 | * While we ack the interrupt interrupts are disabled and thus we don't need |
131 | * to deal with concurrency issues. Same for mips_cpu_irq_end. | 88 | * to deal with concurrency issues. Same for mips_cpu_irq_end. |
@@ -143,10 +100,10 @@ static void mips_mt_cpu_irq_ack(unsigned int irq) | |||
143 | static struct irq_chip mips_mt_cpu_irq_controller = { | 100 | static struct irq_chip mips_mt_cpu_irq_controller = { |
144 | .typename = "MIPS", | 101 | .typename = "MIPS", |
145 | .startup = mips_mt_cpu_irq_startup, | 102 | .startup = mips_mt_cpu_irq_startup, |
146 | .shutdown = mips_mt_cpu_irq_shutdown, | ||
147 | .enable = mips_mt_cpu_irq_enable, | ||
148 | .disable = mips_mt_cpu_irq_disable, | ||
149 | .ack = mips_mt_cpu_irq_ack, | 103 | .ack = mips_mt_cpu_irq_ack, |
104 | .mask = mask_mips_mt_irq, | ||
105 | .mask_ack = mips_mt_cpu_irq_ack, | ||
106 | .unmask = unmask_mips_mt_irq, | ||
150 | .end = mips_mt_cpu_irq_end, | 107 | .end = mips_mt_cpu_irq_end, |
151 | }; | 108 | }; |
152 | 109 | ||
@@ -163,19 +120,11 @@ void __init mips_cpu_irq_init(int irq_base) | |||
163 | * leave them uninitialized for other processors. | 120 | * leave them uninitialized for other processors. |
164 | */ | 121 | */ |
165 | if (cpu_has_mipsmt) | 122 | if (cpu_has_mipsmt) |
166 | for (i = irq_base; i < irq_base + 2; i++) { | 123 | for (i = irq_base; i < irq_base + 2; i++) |
167 | irq_desc[i].status = IRQ_DISABLED; | 124 | set_irq_chip(i, &mips_mt_cpu_irq_controller); |
168 | irq_desc[i].action = NULL; | 125 | |
169 | irq_desc[i].depth = 1; | 126 | for (i = irq_base + 2; i < irq_base + 8; i++) |
170 | irq_desc[i].chip = &mips_mt_cpu_irq_controller; | 127 | set_irq_chip(i, &mips_cpu_irq_controller); |
171 | } | ||
172 | |||
173 | for (i = irq_base + 2; i < irq_base + 8; i++) { | ||
174 | irq_desc[i].status = IRQ_DISABLED; | ||
175 | irq_desc[i].action = NULL; | ||
176 | irq_desc[i].depth = 1; | ||
177 | irq_desc[i].chip = &mips_cpu_irq_controller; | ||
178 | } | ||
179 | 128 | ||
180 | mips_cpu_irq_base = irq_base; | 129 | mips_cpu_irq_base = irq_base; |
181 | } | 130 | } |