[MIPS] Enable support for the userlocal hardware register

Which will cut down the cost of RDHWR $29 which is used to obtain the
TLS pointer and so far being emulated in software down to a single cycle
operation.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 12 insertions, 4 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b12eeee0e974..27fc1843423e 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -588,6 +588,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                 c->options |= MIPS_CPU_VEIC;
         if (config3 & MIPS_CONF3_MT)
                 c->ases |= MIPS_ASE_MIPSMT;
+        if (config3 & MIPS_CONF3_ULRI)
+                c->options |= MIPS_CPU_ULRI;
 
         return config3 & MIPS_CONF_M;
 }
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 9dd5a2df8eac..b947c61c0cc8 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -272,9 +272,8 @@ asmlinkage int sys_set_thread_area(unsigned long addr)
         struct thread_info *ti = task_thread_info(current);
 
         ti->tp_value = addr;
-
-        /* If some future MIPS implementation has this register in hardware,
-         * we will need to update it here (and in context switches).  */
+        if (cpu_has_userlocal)
+                write_c0_userlocal(addr);
 
         return 0;
 }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index c598e890a880..9b19a84d11ef 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1341,7 +1341,14 @@ void __init per_cpu_trap_init(void)
                 set_c0_status(ST0_MX);
 
 #ifdef CONFIG_CPU_MIPSR2
-        write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */
+        if (cpu_has_mips_r2) {
+                unsigned int enable = 0x0000000f;
+
+                if (cpu_has_userlocal)
+                        enable |= (1 << 29);
+
+                write_c0_hwrena(enable);
+        }
 #endif
 
 #ifdef CONFIG_MIPS_MT_SMTC