Merge branch 'master' of /pub/scm/linux/kernel/git/torvalds/linux-2.6

13 files changed, 37 insertions, 77 deletions

diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index 21e6d63eb4d1..0a57f86945f1 100644
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -75,6 +75,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
         cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
         init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
 
+        __raw_writeq(0, cfg);
         __raw_writeq(delta - 1, init);
         __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
 
@@ -122,7 +123,7 @@ void __cpuinit sb1480_clockevent_init(void)
                                   CLOCK_EVT_FEAT_ONESHOT;
         clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
         cd->max_delta_ns        = clockevent_delta2ns(0x7fffff, cd);
-        cd->min_delta_ns        = clockevent_delta2ns(1, cd);
+        cd->min_delta_ns        = clockevent_delta2ns(2, cd);
         cd->rating              = 200;
         cd->irq                 = irq;
         cd->cpumask             = cpumask_of_cpu(cpu);
@@ -143,7 +144,10 @@ void __cpuinit sb1480_clockevent_init(void)
 
         action->handler = sibyte_counter_handler;
         action->flags   = IRQF_DISABLED | IRQF_PERCPU;
+        action->mask    = cpumask_of_cpu(cpu);
         action->name    = name;
         action->dev_id  = cd;
+
+        irq_set_affinity(irq, cpumask_of_cpu(cpu));
         setup_irq(irq, action);
 }
diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index e2029d0fc39b..63ac3ad462bc 100644
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -73,6 +73,7 @@ static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
         cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
         init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
 
+        __raw_writeq(0, cfg);
         __raw_writeq(delta - 1, init);
         __raw_writeq(M_SCD_TIMER_ENABLE, cfg);
 
@@ -121,7 +122,7 @@ void __cpuinit sb1250_clockevent_init(void)
                                   CLOCK_EVT_FEAT_ONESHOT;
         clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
         cd->max_delta_ns        = clockevent_delta2ns(0x7fffff, cd);
-        cd->min_delta_ns        = clockevent_delta2ns(1, cd);
+        cd->min_delta_ns        = clockevent_delta2ns(2, cd);
         cd->rating              = 200;
         cd->irq                 = irq;
         cd->cpumask             = cpumask_of_cpu(cpu);
@@ -142,7 +143,10 @@ void __cpuinit sb1250_clockevent_init(void)
 
         action->handler = sibyte_counter_handler;
         action->flags   = IRQF_DISABLED | IRQF_PERCPU;
+        action->mask    = cpumask_of_cpu(cpu);
         action->name    = name;
         action->dev_id  = cd;
+
+        irq_set_affinity(irq, cpumask_of_cpu(cpu));
         setup_irq(irq, action);
 }
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c8c47a2d1972..5c2794391bf5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -943,6 +943,11 @@ __init void cpu_probe(void)
         }
 
         __cpu_name[cpu] = cpu_to_name(c);
+
+        if (cpu_has_mips_r2)
+                c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
+        else
+                c->srsets = 1;
 }
 
 __init void cpu_report(void)
diff --git a/arch/mips/kernel/csrc-sb1250.c b/arch/mips/kernel/csrc-sb1250.c
index ebb16e668877..92212bbb8e45 100644
--- a/arch/mips/kernel/csrc-sb1250.c
+++ b/arch/mips/kernel/csrc-sb1250.c
@@ -43,7 +43,7 @@ static cycle_t sb1250_hpt_read(void)
 }
 
 struct clocksource bcm1250_clocksource = {
-        .name   = "MIPS",
+        .name   = "bcm1250-counter-3",
         .rating = 200,
         .read   = sb1250_hpt_read,
         .mask   = CLOCKSOURCE_MASK(23),
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index c0f19d638b98..e76a76bf0b3d 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -146,7 +146,7 @@ NESTED(handle_int, PT_SIZE, sp)
         and     k0, ST0_IEP
         bnez    k0, 1f
 
-        mfc0    k0, EP0_EPC
+        mfc0    k0, CP0_EPC
         .set    noreorder
         j       k0
         rfe
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 33506ff25910..5b10ac133ec8 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -430,6 +430,7 @@ asmlinkage int irix_sigprocmask(int how, irix_sigset_t __user *new,
                         break;
 
                 default:
+                        spin_unlock_irq(&current->sighand->siglock);
                         return -EINVAL;
                 }
                 recalc_sigpending();
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 250732883488..971adf6ef4f4 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -44,5 +44,5 @@ void __init rm7k_cpu_irq_init(void)
 
         for (i = base; i < base + 4; i++)
                 set_irq_chip_and_handler(i, &rm7k_irq_controller,
-                                         handle_level_irq);
+                                         handle_percpu_irq);
 }
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index ae83d2df6f31..7b04583bd800 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -104,5 +104,5 @@ void __init rm9k_cpu_irq_init(void)
 
         rm9000_perfcount_irq = base + 1;
         set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
-                                 handle_level_irq);
+                                 handle_percpu_irq);
 }
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 7b66e03b5899..0ee2567b780d 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -116,5 +116,5 @@ void __init mips_cpu_irq_init(void)
 
         for (i = irq_base + 2; i < irq_base + 8; i++)
                 set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
-                                         handle_level_irq);
+                                         handle_percpu_irq);
 }
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index efd2d1314123..6e6e947cce1e 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -60,6 +60,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                       cpu_has_dsp ? " dsp" : "",
                       cpu_has_mipsmt ? " mt" : ""
                 );
+        seq_printf(m, "shadow register sets\t: %d\n",
+                       cpu_data[n].srsets);
 
         sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
                 cpu_has_vce ? "%u" : "not available");
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 118be24224f2..01993ec3368b 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -293,7 +293,7 @@ EXPORT(sysn32_call_table)
         PTR     sys_ni_syscall                  /* 6170, was get_kernel_syms */
         PTR     sys_ni_syscall                  /* was query_module */
         PTR     sys_quotactl
-        PTR     sys_nfsservctl
+        PTR     compat_sys_nfsservctl
         PTR     sys_ni_syscall                  /* res. for getpmsg */
         PTR     sys_ni_syscall                  /* 6175  for putpmsg */
         PTR     sys_ni_syscall                  /* res. for afs_syscall */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index fa500787152d..23e73d0650a3 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1100,59 +1100,6 @@ void *set_except_vector(int n, void *addr)
         return (void *)old_handler;
 }
 
-#ifdef CONFIG_CPU_MIPSR2_SRS
-/*
- * MIPSR2 shadow register set allocation
- * FIXME: SMP...
- */
-
-static struct shadow_registers {
-        /*
-         * Number of shadow register sets supported
-         */
-        unsigned long sr_supported;
-        /*
-         * Bitmap of allocated shadow registers
-         */
-        unsigned long sr_allocated;
-} shadow_registers;
-
-static void mips_srs_init(void)
-{
-        shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
-        printk(KERN_INFO "%ld MIPSR2 register sets available\n",
-               shadow_registers.sr_supported);
-        shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
-}
-
-int mips_srs_max(void)
-{
-        return shadow_registers.sr_supported;
-}
-
-int mips_srs_alloc(void)
-{
-        struct shadow_registers *sr = &shadow_registers;
-        int set;
-
-again:
-        set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
-        if (set >= sr->sr_supported)
-                return -1;
-
-        if (test_and_set_bit(set, &sr->sr_allocated))
-                goto again;
-
-        return set;
-}
-
-void mips_srs_free(int set)
-{
-        struct shadow_registers *sr = &shadow_registers;
-
-        clear_bit(set, &sr->sr_allocated);
-}
-
 static asmlinkage void do_default_vi(void)
 {
         show_regs(get_irq_regs());
@@ -1163,6 +1110,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 {
         unsigned long handler;
         unsigned long old_handler = vi_handlers[n];
+        int srssets = current_cpu_data.srsets;
         u32 *w;
         unsigned char *b;
 
@@ -1178,7 +1126,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 
         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
 
-        if (srs >= mips_srs_max())
+        if (srs >= srssets)
                 panic("Shadow register set %d not supported", srs);
 
         if (cpu_has_veic) {
@@ -1186,7 +1134,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                         board_bind_eic_interrupt(n, srs);
         } else if (cpu_has_vint) {
                 /* SRSMap is only defined if shadow sets are implemented */
-                if (mips_srs_max() > 1)
+                if (srssets > 1)
                         change_c0_srsmap(0xf << n*4, srs << n*4);
         }
 
@@ -1253,14 +1201,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
         return set_vi_srs_handler(n, addr, 0);
 }
 
-#else
-
-static inline void mips_srs_init(void)
-{
-}
-
-#endif /* CONFIG_CPU_MIPSR2_SRS */
-
 /*
  * This is used by native signal handling
  */
@@ -1503,8 +1443,6 @@ void __init trap_init(void)
         else
                 ebase = CAC_BASE;
 
-        mips_srs_init();
-
         per_cpu_trap_init();
 
         /*
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 436a64ff3989..38bd33fa2a23 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -1003,6 +1003,7 @@ static void cleanup_tc(struct tc *tc)
         write_tc_c0_tcstatus(tmp);
 
         write_tc_c0_tchalt(TCHALT_H);
+        mips_ihb();
 
         /* bind it to anything other than VPE1 */
 //      write_tc_c0_tcbind(read_tc_c0_tcbind() & ~TCBIND_CURVPE); // | TCBIND_CURVPE
@@ -1235,9 +1236,12 @@ int vpe_free(vpe_handle vpe)
         settc(t->index);
         write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() & ~VPECONF0_VPA);
 
-        /* mark the TC unallocated and halt'ed */
-        write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
+        /* halt the TC */
         write_tc_c0_tchalt(TCHALT_H);
+        mips_ihb();
+
+        /* mark the TC unallocated */
+        write_tc_c0_tcstatus(read_tc_c0_tcstatus() & ~TCSTATUS_A);
 
         v->state = VPE_STATE_UNUSED;
 
@@ -1533,14 +1537,16 @@ static int __init vpe_module_init(void)
                                 t->pvpe = get_vpe(0);   /* set the parent vpe */
                         }
 
+                        /* halt the TC */
+                        write_tc_c0_tchalt(TCHALT_H);
+                        mips_ihb();
+
                         tmp = read_tc_c0_tcstatus();
 
                         /* mark not activated and not dynamically allocatable */
                         tmp &= ~(TCSTATUS_A | TCSTATUS_DA);
                         tmp |= TCSTATUS_IXMT;   /* interrupt exempt */
                         write_tc_c0_tcstatus(tmp);
-
-                        write_tc_c0_tchalt(TCHALT_H);
                 }
         }