MIPS: Install handlers for software IRQs

BMIPS4350/4380/5000 CMT/SMT all use SW INT0/INT1 for inter-thread
signaling.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/1709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 6 insertions, 8 deletions

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 6e71b284f6c9..191eb52228c4 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -103,14 +103,12 @@ void __init mips_cpu_irq_init(void)
         clear_c0_status(ST0_IM);
         clear_c0_cause(CAUSEF_IP);
 
-        /*
-         * Only MT is using the software interrupts currently, so we just
-         * leave them uninitialized for other processors.
-         */
-        if (cpu_has_mipsmt)
-                for (i = irq_base; i < irq_base + 2; i++)
-                        irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
-                                                 handle_percpu_irq);
+        /* Software interrupts are used for MT/CMT IPI */
+        for (i = irq_base; i < irq_base + 2; i++)
+                irq_set_chip_and_handler(i, cpu_has_mipsmt ?
+                                         &mips_mt_cpu_irq_controller :
+                                         &mips_cpu_irq_controller,
+                                         handle_percpu_irq);
 
         for (i = irq_base + 2; i < irq_base + 8; i++)
                 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,