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authorThomas Gleixner <tglx@linutronix.de>2011-03-27 09:19:28 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-03-29 08:48:07 -0400
commite4ec7989b4e55d9275ebac66230b7dac6dcb1fae (patch)
treeb42cd789681bada83b0051899ed66c1c0e2bbea2 /arch/mips/kernel
parent9efbc3fba2cd7f703b55d72e5168ed4348930442 (diff)
MIPS: Convert the irq functions to the new names
Scripted with coccinelle. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/i8259.c6
-rw-r--r--arch/mips/kernel/irq-gic.c2
-rw-r--r--arch/mips/kernel/irq-gt641xx.c4
-rw-r--r--arch/mips/kernel/irq-msc01.c12
-rw-r--r--arch/mips/kernel/irq-rm7000.c2
-rw-r--r--arch/mips/kernel/irq-rm9000.c4
-rw-r--r--arch/mips/kernel/irq.c2
-rw-r--r--arch/mips/kernel/irq_cpu.c4
-rw-r--r--arch/mips/kernel/irq_txx9.c4
-rw-r--r--arch/mips/kernel/smtc.c2
10 files changed, 23 insertions, 19 deletions
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index e221662bb80c..c018696765d4 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -110,7 +110,7 @@ int i8259A_irq_pending(unsigned int irq)
110void make_8259A_irq(unsigned int irq) 110void make_8259A_irq(unsigned int irq)
111{ 111{
112 disable_irq_nosync(irq); 112 disable_irq_nosync(irq);
113 set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq); 113 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
114 enable_irq(irq); 114 enable_irq(irq);
115} 115}
116 116
@@ -336,8 +336,8 @@ void __init init_i8259_irqs(void)
336 init_8259A(0); 336 init_8259A(0);
337 337
338 for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) { 338 for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
339 set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq); 339 irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
340 set_irq_probe(i); 340 irq_set_probe(i);
341 } 341 }
342 342
343 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2); 343 setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 43cd9628251a..0c527f652196 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -229,7 +229,7 @@ static void __init gic_basic_init(int numintrs, int numvpes,
229 vpe_local_setup(numvpes); 229 vpe_local_setup(numvpes);
230 230
231 for (i = _irqbase; i < (_irqbase + numintrs); i++) 231 for (i = _irqbase; i < (_irqbase + numintrs); i++)
232 set_irq_chip(i, &gic_irq_controller); 232 irq_set_chip(i, &gic_irq_controller);
233} 233}
234 234
235void __init gic_init(unsigned long gic_base_addr, 235void __init gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index 7fd176fa367a..883fc6cead36 100644
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -126,6 +126,6 @@ void __init gt641xx_irq_init(void)
126 * bit31: logical or of bits[25:1]. 126 * bit31: logical or of bits[25:1].
127 */ 127 */
128 for (i = 1; i < 30; i++) 128 for (i = 1; i < 30; i++)
129 set_irq_chip_and_handler(GT641XX_IRQ_BASE + i, 129 irq_set_chip_and_handler(GT641XX_IRQ_BASE + i,
130 &gt641xx_irq_chip, handle_level_irq); 130 &gt641xx_irq_chip, handle_level_irq);
131} 131}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index fc800cd9947e..0c6afeed89d2 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -137,16 +137,20 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
137 137
138 switch (imp->im_type) { 138 switch (imp->im_type) {
139 case MSC01_IRQ_EDGE: 139 case MSC01_IRQ_EDGE:
140 set_irq_chip_and_handler_name(irqbase + n, 140 irq_set_chip_and_handler_name(irqbase + n,
141 &msc_edgeirq_type, handle_edge_irq, "edge"); 141 &msc_edgeirq_type,
142 handle_edge_irq,
143 "edge");
142 if (cpu_has_veic) 144 if (cpu_has_veic)
143 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
144 else 146 else
145 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 147 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
146 break; 148 break;
147 case MSC01_IRQ_LEVEL: 149 case MSC01_IRQ_LEVEL:
148 set_irq_chip_and_handler_name(irqbase+n, 150 irq_set_chip_and_handler_name(irqbase + n,
149 &msc_levelirq_type, handle_level_irq, "level"); 151 &msc_levelirq_type,
152 handle_level_irq,
153 "level");
150 if (cpu_has_veic) 154 if (cpu_has_veic)
151 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 155 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
152 else 156 else
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index fd24fd98b041..a8a8977d5887 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -45,6 +45,6 @@ void __init rm7k_cpu_irq_init(void)
45 clear_c0_intcontrol(0x00000f00); /* Mask all */ 45 clear_c0_intcontrol(0x00000f00); /* Mask all */
46 46
47 for (i = base; i < base + 4; i++) 47 for (i = base; i < base + 4; i++)
48 set_irq_chip_and_handler(i, &rm7k_irq_controller, 48 irq_set_chip_and_handler(i, &rm7k_irq_controller,
49 handle_percpu_irq); 49 handle_percpu_irq);
50} 50}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index ca463ec9bad5..38874a4b9255 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -98,10 +98,10 @@ void __init rm9k_cpu_irq_init(void)
98 clear_c0_intcontrol(0x0000f000); /* Mask all */ 98 clear_c0_intcontrol(0x0000f000); /* Mask all */
99 99
100 for (i = base; i < base + 4; i++) 100 for (i = base; i < base + 4; i++)
101 set_irq_chip_and_handler(i, &rm9k_irq_controller, 101 irq_set_chip_and_handler(i, &rm9k_irq_controller,
102 handle_level_irq); 102 handle_level_irq);
103 103
104 rm9000_perfcount_irq = base + 1; 104 rm9000_perfcount_irq = base + 1;
105 set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq, 105 irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
106 handle_percpu_irq); 106 handle_percpu_irq);
107} 107}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 1b68ebe1b458..9b734d74ae8e 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -102,7 +102,7 @@ void __init init_IRQ(void)
102#endif 102#endif
103 103
104 for (i = 0; i < NR_IRQS; i++) 104 for (i = 0; i < NR_IRQS; i++)
105 set_irq_noprobe(i); 105 irq_set_noprobe(i);
106 106
107 arch_init_irq(); 107 arch_init_irq();
108 108
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index fd945c56bc33..6e71b284f6c9 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -109,10 +109,10 @@ void __init mips_cpu_irq_init(void)
109 */ 109 */
110 if (cpu_has_mipsmt) 110 if (cpu_has_mipsmt)
111 for (i = irq_base; i < irq_base + 2; i++) 111 for (i = irq_base; i < irq_base + 2; i++)
112 set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller, 112 irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
113 handle_percpu_irq); 113 handle_percpu_irq);
114 114
115 for (i = irq_base + 2; i < irq_base + 8; i++) 115 for (i = irq_base + 2; i < irq_base + 8; i++)
116 set_irq_chip_and_handler(i, &mips_cpu_irq_controller, 116 irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
117 handle_percpu_irq); 117 handle_percpu_irq);
118} 118}
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
index 526e1581549a..b0c55b50218e 100644
--- a/arch/mips/kernel/irq_txx9.c
+++ b/arch/mips/kernel/irq_txx9.c
@@ -154,8 +154,8 @@ void __init txx9_irq_init(unsigned long baseaddr)
154 for (i = 0; i < TXx9_MAX_IR; i++) { 154 for (i = 0; i < TXx9_MAX_IR; i++) {
155 txx9irq[i].level = 4; /* middle level */ 155 txx9irq[i].level = 4; /* middle level */
156 txx9irq[i].mode = TXx9_IRCR_LOW; 156 txx9irq[i].mode = TXx9_IRCR_LOW;
157 set_irq_chip_and_handler(TXX9_IRQ_BASE + i, 157 irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip,
158 &txx9_irq_chip, handle_level_irq); 158 handle_level_irq);
159 } 159 }
160 160
161 /* mask all IRC interrupts */ 161 /* mask all IRC interrupts */
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f7e2c7807d7b..5a88cc4ccd5a 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1146,7 +1146,7 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe)
1146 1146
1147 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ)); 1147 setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
1148 1148
1149 set_irq_handler(cpu_ipi_irq, handle_percpu_irq); 1149 irq_set_handler(cpu_ipi_irq, handle_percpu_irq);
1150} 1150}
1151 1151
1152/* 1152/*