MIPS: Netlogic: XLP CPU support.

Add support for Netlogic's XLP MIPS SoC. This patch adds:
* XLP processor ID in cpu_probe.c and asm/cpu.h
* XLP case to asm/module.h
* CPU_XLP case to mm/tlbex.c
* minor change to r4k cache handling to ignore XLP secondary cache
* XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2966/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 16 insertions, 3 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index aa20382b9305..92fae7f459cf 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -192,6 +192,7 @@ void __init check_wait(void)
         case CPU_CAVIUM_OCTEON2:
         case CPU_JZRISC:
         case CPU_XLR:
+        case CPU_XLP:
                 cpu_wait = r4k_wait;
                 break;
 
@@ -1024,6 +1025,11 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
                         MIPS_CPU_LLSC);
 
         switch (c->processor_id & 0xff00) {
+        case PRID_IMP_NETLOGIC_XLP832:
+                c->cputype = CPU_XLP;
+                __cpu_name[cpu] = "Netlogic XLP";
+                break;
+
         case PRID_IMP_NETLOGIC_XLR732:
         case PRID_IMP_NETLOGIC_XLR716:
         case PRID_IMP_NETLOGIC_XLR532:
@@ -1054,14 +1060,21 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
                 break;
 
         default:
-                printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
+                pr_info("Unknown Netlogic chip id [%02x]!\n",
                        c->processor_id);
                 c->cputype = CPU_XLR;
                 break;
         }
 
-        c->isa_level = MIPS_CPU_ISA_M64R1;
-        c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+        if (c->cputype == CPU_XLP) {
+                c->isa_level = MIPS_CPU_ISA_M64R2;
+                c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
+                /* This will be updated again after all threads are woken up */
+                c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+        } else {
+                c->isa_level = MIPS_CPU_ISA_M64R1;
+                c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
+        }
 }
 
 #ifdef CONFIG_64BIT