Revert "MIPS: Allow ASID size to be determined at boot time."

This reverts commit d532f3d26716a39dfd4b88d687bd344fbe77e390.

The original commit has several problems:

1) Doesn't work with 64-bit kernels.

2) Calls TLBMISS_HANDLER_SETUP() before the code is generated.

3) Calls TLBMISS_HANDLER_SETUP() twice in per_cpu_trap_init() when
   only one call is needed.

[ralf@linux-mips.org: Also revert the bits of the ASID patch which were
hidden in the KVM merge.]

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/5242/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

3 files changed, 8 insertions, 10 deletions

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 5c2ba9f08a80..9098829bfcb0 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -493,7 +493,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
         .set    noreorder
         /* check if TLB contains a entry for EPC */
         MFC0    k1, CP0_ENTRYHI
-        andi    k1, 0xff        /* ASID_MASK patched at run-time!! */
+        andi    k1, 0xff        /* ASID_MASK */
         MFC0    k0, CP0_EPC
         PTR_SRL k0, _PAGE_SHIFT + 1
         PTR_SLL k0, _PAGE_SHIFT + 1
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 31d22f3121c9..7186222dc5bb 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -111,7 +111,7 @@ static int vpe0limit;
 static int ipibuffers;
 static int nostlb;
 static int asidmask;
-unsigned int smtc_asid_mask = 0xff;
+unsigned long smtc_asid_mask = 0xff;
 
 static int __init vpe0tcs(char *str)
 {
@@ -1395,7 +1395,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
         asid = asid_cache(cpu);
 
         do {
-                if (!ASID_MASK(ASID_INC(asid))) {
+                if (!((asid += ASID_INC) & ASID_MASK) ) {
                         if (cpu_has_vtag_icache)
                                 flush_icache_all();
                         /* Traverse all online CPUs (hack requires contiguous range) */
@@ -1414,7 +1414,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
                                                 mips_ihb();
                                         }
                                         tcstat = read_tc_c0_tcstatus();
-                                        smtc_live_asid[tlb][ASID_MASK(tcstat)] |= (asiduse)(0x1 << i);
+                                        smtc_live_asid[tlb][(tcstat & ASID_MASK)] |= (asiduse)(0x1 << i);
                                         if (!prevhalt)
                                                 write_tc_c0_tchalt(0);
                                 }
@@ -1423,7 +1423,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
                                 asid = ASID_FIRST_VERSION;
                         local_flush_tlb_all();  /* start new asid cycle */
                 }
-        } while (smtc_live_asid[tlb][ASID_MASK(asid)]);
+        } while (smtc_live_asid[tlb][(asid & ASID_MASK)]);
 
         /*
          * SMTC shares the TLB within VPEs and possibly across all VPEs.
@@ -1461,7 +1461,7 @@ void smtc_flush_tlb_asid(unsigned long asid)
                 tlb_read();
                 ehb();
                 ehi = read_c0_entryhi();
-                if (ASID_MASK(ehi) == asid) {
+                if ((ehi & ASID_MASK) == asid) {
                     /*
                      * Invalidate only entries with specified ASID,
                      * makiing sure all entries differ.
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 77cff1f6d050..cb14db3c5764 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1656,7 +1656,6 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
         unsigned int cpu = smp_processor_id();
         unsigned int status_set = ST0_CU0;
         unsigned int hwrena = cpu_hwrena_impl_bits;
-        unsigned long asid = 0;
 #ifdef CONFIG_MIPS_MT_SMTC
         int secondaryTC = 0;
         int bootTC = (cpu == 0);
@@ -1740,9 +1739,8 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
         }
 #endif /* CONFIG_MIPS_MT_SMTC */
 
-        asid = ASID_FIRST_VERSION;
-        cpu_data[cpu].asid_cache = asid;
-        TLBMISS_HANDLER_SETUP();
+        if (!cpu_data[cpu].asid_cache)
+                cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
 
         atomic_inc(&init_mm.mm_count);
         current->active_mm = &init_mm;