Merge branch 'x86/urgent' into x86/apic

Conflicts:
	arch/x86/mach-default/setup.c

Semantic merge:
	arch/x86/kernel/irqinit_32.c

Signed-off-by: Ingo Molnar <mingo@elte.hu>

3 files changed, 20 insertions, 5 deletions

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index fb6f73148df2..8882e5766f27 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -458,7 +458,11 @@ NESTED(nmi_handler, PT_SIZE, sp)
         BUILD_HANDLER fpe fpe fpe silent                /* #15 */
         BUILD_HANDLER mdmx mdmx sti silent              /* #22 */
 #ifdef  CONFIG_HARDWARE_WATCHPOINTS
-        BUILD_HANDLER watch watch sti silent            /* #23 */
+        /*
+         * For watch, interrupts will be enabled after the watch
+         * registers are read.
+         */
+        BUILD_HANDLER watch watch cli silent            /* #23 */
 #else
         BUILD_HANDLER watch watch sti verbose           /* #23 */
 #endif
diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index 5e77a3a21f98..42461310b185 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -79,7 +79,8 @@ asmlinkage long mipsmt_sys_sched_setaffinity(pid_t pid, unsigned int len,
 
         euid = current_euid();
         retval = -EPERM;
-        if (euid != p->euid && euid != p->uid && !capable(CAP_SYS_NICE)) {
+        if (euid != p->cred->euid && euid != p->cred->uid &&
+            !capable(CAP_SYS_NICE)) {
                 read_unlock(&tasklist_lock);
                 goto out_unlock;
         }
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f6083c6bfaa4..b2d7041341b8 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -944,6 +944,9 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
         force_sig(SIGILL, current);
 }
 
+/*
+ * Called with interrupts disabled.
+ */
 asmlinkage void do_watch(struct pt_regs *regs)
 {
         u32 cause;
@@ -963,9 +966,12 @@ asmlinkage void do_watch(struct pt_regs *regs)
          */
         if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
                 mips_read_watch_registers();
+                local_irq_enable();
                 force_sig(SIGTRAP, current);
-        } else
+        } else {
                 mips_clear_watch_registers();
+                local_irq_enable();
+        }
 }
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
@@ -1582,7 +1588,11 @@ void __init set_handler(unsigned long offset, void *addr, unsigned long size)
 static char panic_null_cerr[] __cpuinitdata =
         "Trying to set NULL cache error exception handler";
 
-/* Install uncached CPU exception handler */
+/*
+ * Install uncached CPU exception handler.
+ * This is suitable only for the cache error exception which is the only
+ * exception handler that is being run uncached.
+ */
 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
         unsigned long size)
 {
@@ -1593,7 +1603,7 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
         unsigned long uncached_ebase = TO_UNCAC(ebase);
 #endif
         if (cpu_has_mips_r2)
-                ebase += (read_c0_ebase() & 0x3ffff000);
+                uncached_ebase += (read_c0_ebase() & 0x3ffff000);
 
         if (!addr)
                 panic(panic_null_cerr);