diff options
| author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-23 17:08:59 -0400 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2011-03-25 13:45:17 -0400 |
| commit | e15883da8a8b83c73bf1ba030cddeb2cfd92a555 (patch) | |
| tree | f46ce0109ea46a043d75a5ac240209494fb6e14a /arch/mips/kernel | |
| parent | aa400ae5ecaeab00336fdedf51f58c017e5f2274 (diff) | |
MIPS: MSC01: Convert to new irq_chip functions
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2188/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/irq-msc01.c | 51 |
1 files changed, 24 insertions, 27 deletions
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c index 6a8cd28133d5..fc800cd9947e 100644 --- a/arch/mips/kernel/irq-msc01.c +++ b/arch/mips/kernel/irq-msc01.c | |||
| @@ -28,8 +28,10 @@ static unsigned long _icctrl_msc; | |||
| 28 | static unsigned int irq_base; | 28 | static unsigned int irq_base; |
| 29 | 29 | ||
| 30 | /* mask off an interrupt */ | 30 | /* mask off an interrupt */ |
| 31 | static inline void mask_msc_irq(unsigned int irq) | 31 | static inline void mask_msc_irq(struct irq_data *d) |
| 32 | { | 32 | { |
| 33 | unsigned int irq = d->irq; | ||
| 34 | |||
| 33 | if (irq < (irq_base + 32)) | 35 | if (irq < (irq_base + 32)) |
| 34 | MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); | 36 | MSCIC_WRITE(MSC01_IC_DISL, 1<<(irq - irq_base)); |
| 35 | else | 37 | else |
| @@ -37,8 +39,10 @@ static inline void mask_msc_irq(unsigned int irq) | |||
| 37 | } | 39 | } |
| 38 | 40 | ||
| 39 | /* unmask an interrupt */ | 41 | /* unmask an interrupt */ |
| 40 | static inline void unmask_msc_irq(unsigned int irq) | 42 | static inline void unmask_msc_irq(struct irq_data *d) |
| 41 | { | 43 | { |
| 44 | unsigned int irq = d->irq; | ||
| 45 | |||
| 42 | if (irq < (irq_base + 32)) | 46 | if (irq < (irq_base + 32)) |
| 43 | MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); | 47 | MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base)); |
| 44 | else | 48 | else |
| @@ -48,9 +52,11 @@ static inline void unmask_msc_irq(unsigned int irq) | |||
| 48 | /* | 52 | /* |
| 49 | * Masks and ACKs an IRQ | 53 | * Masks and ACKs an IRQ |
| 50 | */ | 54 | */ |
| 51 | static void level_mask_and_ack_msc_irq(unsigned int irq) | 55 | static void level_mask_and_ack_msc_irq(struct irq_data *d) |
| 52 | { | 56 | { |
| 53 | mask_msc_irq(irq); | 57 | unsigned int irq = d->irq; |
| 58 | |||
| 59 | mask_msc_irq(d); | ||
| 54 | if (!cpu_has_veic) | 60 | if (!cpu_has_veic) |
| 55 | MSCIC_WRITE(MSC01_IC_EOI, 0); | 61 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
| 56 | /* This actually needs to be a call into platform code */ | 62 | /* This actually needs to be a call into platform code */ |
| @@ -60,9 +66,11 @@ static void level_mask_and_ack_msc_irq(unsigned int irq) | |||
| 60 | /* | 66 | /* |
| 61 | * Masks and ACKs an IRQ | 67 | * Masks and ACKs an IRQ |
| 62 | */ | 68 | */ |
| 63 | static void edge_mask_and_ack_msc_irq(unsigned int irq) | 69 | static void edge_mask_and_ack_msc_irq(struct irq_data *d) |
| 64 | { | 70 | { |
| 65 | mask_msc_irq(irq); | 71 | unsigned int irq = d->irq; |
| 72 | |||
| 73 | mask_msc_irq(d); | ||
| 66 | if (!cpu_has_veic) | 74 | if (!cpu_has_veic) |
| 67 | MSCIC_WRITE(MSC01_IC_EOI, 0); | 75 | MSCIC_WRITE(MSC01_IC_EOI, 0); |
| 68 | else { | 76 | else { |
| @@ -75,15 +83,6 @@ static void edge_mask_and_ack_msc_irq(unsigned int irq) | |||
| 75 | } | 83 | } |
| 76 | 84 | ||
| 77 | /* | 85 | /* |
| 78 | * End IRQ processing | ||
| 79 | */ | ||
| 80 | static void end_msc_irq(unsigned int irq) | ||
| 81 | { | ||
| 82 | if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) | ||
| 83 | unmask_msc_irq(irq); | ||
| 84 | } | ||
| 85 | |||
| 86 | /* | ||
| 87 | * Interrupt handler for interrupts coming from SOC-it. | 86 | * Interrupt handler for interrupts coming from SOC-it. |
| 88 | */ | 87 | */ |
| 89 | void ll_msc_irq(void) | 88 | void ll_msc_irq(void) |
| @@ -107,22 +106,20 @@ static void msc_bind_eic_interrupt(int irq, int set) | |||
| 107 | 106 | ||
| 108 | static struct irq_chip msc_levelirq_type = { | 107 | static struct irq_chip msc_levelirq_type = { |
| 109 | .name = "SOC-it-Level", | 108 | .name = "SOC-it-Level", |
| 110 | .ack = level_mask_and_ack_msc_irq, | 109 | .irq_ack = level_mask_and_ack_msc_irq, |
| 111 | .mask = mask_msc_irq, | 110 | .irq_mask = mask_msc_irq, |
| 112 | .mask_ack = level_mask_and_ack_msc_irq, | 111 | .irq_mask_ack = level_mask_and_ack_msc_irq, |
| 113 | .unmask = unmask_msc_irq, | 112 | .irq_unmask = unmask_msc_irq, |
| 114 | .eoi = unmask_msc_irq, | 113 | .irq_eoi = unmask_msc_irq, |
| 115 | .end = end_msc_irq, | ||
| 116 | }; | 114 | }; |
| 117 | 115 | ||
| 118 | static struct irq_chip msc_edgeirq_type = { | 116 | static struct irq_chip msc_edgeirq_type = { |
| 119 | .name = "SOC-it-Edge", | 117 | .name = "SOC-it-Edge", |
| 120 | .ack = edge_mask_and_ack_msc_irq, | 118 | .irq_ack = edge_mask_and_ack_msc_irq, |
| 121 | .mask = mask_msc_irq, | 119 | .irq_mask = mask_msc_irq, |
| 122 | .mask_ack = edge_mask_and_ack_msc_irq, | 120 | .irq_mask_ack = edge_mask_and_ack_msc_irq, |
| 123 | .unmask = unmask_msc_irq, | 121 | .irq_unmask = unmask_msc_irq, |
| 124 | .eoi = unmask_msc_irq, | 122 | .irq_eoi = unmask_msc_irq, |
| 125 | .end = end_msc_irq, | ||
| 126 | }; | 123 | }; |
| 127 | 124 | ||
| 128 | 125 | ||
