[PATCH] mips: clean up 32/64-bit configuration

Start cleaning 32-bit vs. 64-bit configuration.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 6 insertions, 6 deletions

diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 3f24a1d45865..36c5212e0928 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -240,7 +240,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 break;
 
         case lwu_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 /*
                  * A 32-bit kernel might be running on a 64-bit processor.  But
                  * if we're on a 32-bit processor and an i-cache incoherency
@@ -278,13 +278,13 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 *newvalue = value;
                 *regptr = &regs->regs[insn.i_format.rt];
                 break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
                 /* Cannot handle 64-bit instructions in 32-bit kernel */
                 goto sigill;
 
         case ld_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 /*
                  * A 32-bit kernel might be running on a 64-bit processor.  But
                  * if we're on a 32-bit processor and an i-cache incoherency
@@ -320,7 +320,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 *newvalue = value;
                 *regptr = &regs->regs[insn.i_format.rt];
                 break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
                 /* Cannot handle 64-bit instructions in 32-bit kernel */
                 goto sigill;
@@ -392,7 +392,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 break;
 
         case sd_op:
-#ifdef CONFIG_MIPS64
+#ifdef CONFIG_64BIT
                 /*
                  * A 32-bit kernel might be running on a 64-bit processor.  But
                  * if we're on a 32-bit processor and an i-cache incoherency
@@ -428,7 +428,7 @@ static inline int emulate_load_store_insn(struct pt_regs *regs,
                 if (res)
                         goto fault;
                 break;
-#endif /* CONFIG_MIPS64 */
+#endif /* CONFIG_64BIT */
 
                 /* Cannot handle 64-bit instructions in 32-bit kernel */
                 goto sigill;