Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
  [MIPS] N32 needs to use the compat version of sys_nfsservctl.
  [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.
  [MIPS] Sibyte: Fix name of clocksource.
  [MIPS] SNI: s/achknowledge/acknowledge/
  [MIPS] Makefile: Fix canonical system names
  [MIPS] vpe: handle halting TCs in an errata safe way.
  [MIPS] Sibyte: Stop timers before programming next even.
  [MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.
  [MIPS] Lasat: Fix overlap of interrupt number ranges.
  [MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1
  [MIPS] Fix shadow register support.
  [MIPS] Change get_cycles to always return 0.
  [MIPS] Fix typo in R3000 TRACE_IRQFLAGS code
  [MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.
  [MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHz
  [MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.
  [MIPS] Sibyte: pin timer interrupt to their cores.
  [MIPS] Qemu: Add early printk, your friend in a cold night.
  [MIPS] Convert reference to mem_map to pfn_to_page().
  [MIPS] Sibyte: resurrect old cache hack.

1 files changed, 3 insertions, 65 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index fa500787152d..23e73d0650a3 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1100,59 +1100,6 @@ void *set_except_vector(int n, void *addr)
         return (void *)old_handler;
 }
 
-#ifdef CONFIG_CPU_MIPSR2_SRS
-/*
- * MIPSR2 shadow register set allocation
- * FIXME: SMP...
- */
-
-static struct shadow_registers {
-        /*
-         * Number of shadow register sets supported
-         */
-        unsigned long sr_supported;
-        /*
-         * Bitmap of allocated shadow registers
-         */
-        unsigned long sr_allocated;
-} shadow_registers;
-
-static void mips_srs_init(void)
-{
-        shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
-        printk(KERN_INFO "%ld MIPSR2 register sets available\n",
-               shadow_registers.sr_supported);
-        shadow_registers.sr_allocated = 1;      /* Set 0 used by kernel */
-}
-
-int mips_srs_max(void)
-{
-        return shadow_registers.sr_supported;
-}
-
-int mips_srs_alloc(void)
-{
-        struct shadow_registers *sr = &shadow_registers;
-        int set;
-
-again:
-        set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
-        if (set >= sr->sr_supported)
-                return -1;
-
-        if (test_and_set_bit(set, &sr->sr_allocated))
-                goto again;
-
-        return set;
-}
-
-void mips_srs_free(int set)
-{
-        struct shadow_registers *sr = &shadow_registers;
-
-        clear_bit(set, &sr->sr_allocated);
-}
-
 static asmlinkage void do_default_vi(void)
 {
         show_regs(get_irq_regs());
@@ -1163,6 +1110,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 {
         unsigned long handler;
         unsigned long old_handler = vi_handlers[n];
+        int srssets = current_cpu_data.srsets;
         u32 *w;
         unsigned char *b;
 
@@ -1178,7 +1126,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 
         b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
 
-        if (srs >= mips_srs_max())
+        if (srs >= srssets)
                 panic("Shadow register set %d not supported", srs);
 
         if (cpu_has_veic) {
@@ -1186,7 +1134,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                         board_bind_eic_interrupt(n, srs);
         } else if (cpu_has_vint) {
                 /* SRSMap is only defined if shadow sets are implemented */
-                if (mips_srs_max() > 1)
+                if (srssets > 1)
                         change_c0_srsmap(0xf << n*4, srs << n*4);
         }
 
@@ -1253,14 +1201,6 @@ void *set_vi_handler(int n, vi_handler_t addr)
         return set_vi_srs_handler(n, addr, 0);
 }
 
-#else
-
-static inline void mips_srs_init(void)
-{
-}
-
-#endif /* CONFIG_CPU_MIPSR2_SRS */
-
 /*
  * This is used by native signal handling
  */
@@ -1503,8 +1443,6 @@ void __init trap_init(void)
         else
                 ebase = CAC_BASE;
 
-        mips_srs_init();
-
         per_cpu_trap_init();
 
         /*