MIPS: MT: Remove SMTC support

Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.

Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 0 insertions, 63 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 074e857ced28..3a2672907f80 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -370,9 +370,6 @@ void __noreturn die(const char *str, struct pt_regs *regs)
 {
         static int die_counter;
         int sig = SIGSEGV;
-#ifdef CONFIG_MIPS_MT_SMTC
-        unsigned long dvpret;
-#endif /* CONFIG_MIPS_MT_SMTC */
 
         oops_enter();
 
@@ -382,13 +379,7 @@ void __noreturn die(const char *str, struct pt_regs *regs)
 
         console_verbose();
         raw_spin_lock_irq(&die_lock);
-#ifdef CONFIG_MIPS_MT_SMTC
-        dvpret = dvpe();
-#endif /* CONFIG_MIPS_MT_SMTC */
         bust_spinlocks(1);
-#ifdef CONFIG_MIPS_MT_SMTC
-        mips_mt_regdump(dvpret);
-#endif /* CONFIG_MIPS_MT_SMTC */
 
         printk("%s[#%d]:\n", str, ++die_counter);
         show_registers(regs);
@@ -1759,19 +1750,6 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
                 extern char rollback_except_vec_vi;
                 char *vec_start = using_rollback_handler() ?
                         &rollback_except_vec_vi : &except_vec_vi;
-#ifdef CONFIG_MIPS_MT_SMTC
-                /*
-                 * We need to provide the SMTC vectored interrupt handler
-                 * not only with the address of the handler, but with the
-                 * Status.IM bit to be masked before going there.
-                 */
-                extern char except_vec_vi_mori;
-#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
-                const int mori_offset = &except_vec_vi_mori - vec_start + 2;
-#else
-                const int mori_offset = &except_vec_vi_mori - vec_start;
-#endif
-#endif /* CONFIG_MIPS_MT_SMTC */
 #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
                 const int lui_offset = &except_vec_vi_lui - vec_start + 2;
                 const int ori_offset = &except_vec_vi_ori - vec_start + 2;
@@ -1795,12 +1773,6 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
 #else
                                 handler_len);
 #endif
-#ifdef CONFIG_MIPS_MT_SMTC
-                BUG_ON(n > 7);  /* Vector index %d exceeds SMTC maximum. */
-
-                h = (u16 *)(b + mori_offset);
-                *h = (0x100 << n);
-#endif /* CONFIG_MIPS_MT_SMTC */
                 h = (u16 *)(b + lui_offset);
                 *h = (handler >> 16) & 0xffff;
                 h = (u16 *)(b + ori_offset);
@@ -1870,20 +1842,6 @@ void per_cpu_trap_init(bool is_boot_cpu)
         unsigned int cpu = smp_processor_id();
         unsigned int status_set = ST0_CU0;
         unsigned int hwrena = cpu_hwrena_impl_bits;
-#ifdef CONFIG_MIPS_MT_SMTC
-        int secondaryTC = 0;
-        int bootTC = (cpu == 0);
-
-        /*
-         * Only do per_cpu_trap_init() for first TC of Each VPE.
-         * Note that this hack assumes that the SMTC init code
-         * assigns TCs consecutively and in ascending order.
-         */
-
-        if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
-            ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
-                secondaryTC = 1;
-#endif /* CONFIG_MIPS_MT_SMTC */
 
         /*
          * Disable coprocessors and select 32-bit or 64-bit addressing
@@ -1911,10 +1869,6 @@ void per_cpu_trap_init(bool is_boot_cpu)
         if (hwrena)
                 write_c0_hwrena(hwrena);
 
-#ifdef CONFIG_MIPS_MT_SMTC
-        if (!secondaryTC) {
-#endif /* CONFIG_MIPS_MT_SMTC */
-
         if (cpu_has_veic || cpu_has_vint) {
                 unsigned long sr = set_c0_status(ST0_BEV);
                 write_c0_ebase(ebase);
@@ -1949,10 +1903,6 @@ void per_cpu_trap_init(bool is_boot_cpu)
                 cp0_perfcount_irq = -1;
         }
 
-#ifdef CONFIG_MIPS_MT_SMTC
-        }
-#endif /* CONFIG_MIPS_MT_SMTC */
-
         if (!cpu_data[cpu].asid_cache)
                 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
 
@@ -1961,23 +1911,10 @@ void per_cpu_trap_init(bool is_boot_cpu)
         BUG_ON(current->mm);
         enter_lazy_tlb(&init_mm, current);
 
-#ifdef CONFIG_MIPS_MT_SMTC
-        if (bootTC) {
-#endif /* CONFIG_MIPS_MT_SMTC */
                 /* Boot CPU's cache setup in setup_arch(). */
                 if (!is_boot_cpu)
                         cpu_cache_init();
                 tlb_init();
-#ifdef CONFIG_MIPS_MT_SMTC
-        } else if (!secondaryTC) {
-                /*
-                 * First TC in non-boot VPE must do subset of tlb_init()
-                 * for MMU countrol registers.
-                 */
-                write_c0_pagemask(PM_DEFAULT_MASK);
-                write_c0_wired(0);
-        }
-#endif /* CONFIG_MIPS_MT_SMTC */
         TLBMISS_HANDLER_SETUP();
 }