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authorRalf Baechle <ralf@linux-mips.org>2005-08-17 09:44:26 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:32:09 -0400
commitd03d0a57754cb820d318d2234c60b728eb38a94d (patch)
treec9feac8689e0081304382411592f3e074fe96502 /arch/mips/kernel/traps.c
parent533330bf7fa19854f3b4accd2b84ff58e3ee160f (diff)
MT bulletproofing.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r--arch/mips/kernel/traps.c10
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 519b8f18eedf..876aff71cd2e 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1186,8 +1186,14 @@ void __init per_cpu_trap_init(void)
1186 /* Setting vector spacing enables EI/VI mode */ 1186 /* Setting vector spacing enables EI/VI mode */
1187 change_c0_intctl (0x3e0, VECTORSPACING); 1187 change_c0_intctl (0x3e0, VECTORSPACING);
1188 } 1188 }
1189 if (cpu_has_divec) 1189 if (cpu_has_divec) {
1190 set_c0_cause(CAUSEF_IV); 1190 if (cpu_has_mipsmt) {
1191 unsigned int vpflags = dvpe();
1192 set_c0_cause(CAUSEF_IV);
1193 evpe(vpflags);
1194 } else
1195 set_c0_cause(CAUSEF_IV);
1196 }
1191 1197
1192 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 1198 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1193 TLBMISS_HANDLER_SETUP(); 1199 TLBMISS_HANDLER_SETUP();