diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:15 -0400 |
commit | 10cc3529072d5415fb040018a8a99aa7a60190b6 (patch) | |
tree | fe07fb5112c9c34c2aecfac982155307bc168f07 /arch/mips/kernel/traps.c | |
parent | aeffdbbaff133b0c3989e20af5baa091d3d0b409 (diff) |
[MIPS] Allow hardwiring of the CPU type to a single type for optimization.
This saves a few k on systems which only ever ship with a single CPU type.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r-- | arch/mips/kernel/traps.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index d96f8218a91e..ac762d8d802d 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c | |||
@@ -954,7 +954,7 @@ asmlinkage void do_reserved(struct pt_regs *regs) | |||
954 | */ | 954 | */ |
955 | static inline void parity_protection_init(void) | 955 | static inline void parity_protection_init(void) |
956 | { | 956 | { |
957 | switch (current_cpu_data.cputype) { | 957 | switch (current_cpu_type()) { |
958 | case CPU_24K: | 958 | case CPU_24K: |
959 | case CPU_34K: | 959 | case CPU_34K: |
960 | case CPU_5KC: | 960 | case CPU_5KC: |
@@ -1549,8 +1549,8 @@ void __init trap_init(void) | |||
1549 | set_except_vector(12, handle_ov); | 1549 | set_except_vector(12, handle_ov); |
1550 | set_except_vector(13, handle_tr); | 1550 | set_except_vector(13, handle_tr); |
1551 | 1551 | ||
1552 | if (current_cpu_data.cputype == CPU_R6000 || | 1552 | if (current_cpu_type() == CPU_R6000 || |
1553 | current_cpu_data.cputype == CPU_R6000A) { | 1553 | current_cpu_type() == CPU_R6000A) { |
1554 | /* | 1554 | /* |
1555 | * The R6000 is the only R-series CPU that features a machine | 1555 | * The R6000 is the only R-series CPU that features a machine |
1556 | * check exception (similar to the R4000 cache error) and | 1556 | * check exception (similar to the R4000 cache error) and |