MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs

The MIPS processor is limited to 64 external interrupt sources. Using a
greater number without IRQ sharing requires reading platform-specific
registers. On such platforms, reading the IntCtl register to determine
which interrupt corresponds to a timer interrupt will not work.

On MIPSR2 systems there is a solution - the TI bit in the Cause register,
specifically indicates that a timer interrupt has occured. This patch uses
that bit to detect interrupts for MIPSR2 processors, which may be expected
to work regardless of how the timer interrupt may be routed in the hardware.

Signed-off-by: David VomLehn (dvomlehn@cisco.com)
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/804/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

1 files changed, 4 insertions, 2 deletions

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 308e43460864..338dfe8ed002 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1403,6 +1403,7 @@ extern void flush_tlb_handlers(void);
  * Timer interrupt
  */
 int cp0_compare_irq;
+int cp0_compare_irq_shift;
 
 /*
  * Performance counter IRQ or -1 if shared with timer
@@ -1493,8 +1494,9 @@ void __cpuinit per_cpu_trap_init(void)
          *  o read IntCtl.IPPCI to determine the performance counter interrupt
          */
         if (cpu_has_mips_r2) {
-                cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
-                cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
+                cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
+                cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
+                cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
                 if (cp0_perfcount_irq == cp0_compare_irq)
                         cp0_perfcount_irq = -1;
         } else {