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authorRalf Baechle <ralf@linux-mips.org>2006-06-05 12:24:46 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-06-29 16:10:51 -0400
commitf41ae0b2b9e5b4455cfc68dcc885f4fa2a973384 (patch)
tree1d571a10b4265233b511ce2f45d4ca03b9fbb13a /arch/mips/kernel/traps.c
parente73ea273ef87a04ff59fc368fa33333dca275dde (diff)
[MIPS] Fix configuration of R2 CPU features and multithreading.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r--arch/mips/kernel/traps.c15
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ad16eceb24dd..67971938a2cb 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1050,7 +1050,7 @@ void *set_except_vector(int n, void *addr)
1050 return (void *)old_handler; 1050 return (void *)old_handler;
1051} 1051}
1052 1052
1053#ifdef CONFIG_CPU_MIPSR2 1053#ifdef CONFIG_CPU_MIPSR2_SRS
1054/* 1054/*
1055 * MIPSR2 shadow register set allocation 1055 * MIPSR2 shadow register set allocation
1056 * FIXME: SMP... 1056 * FIXME: SMP...
@@ -1069,11 +1069,9 @@ static struct shadow_registers {
1069 1069
1070static void mips_srs_init(void) 1070static void mips_srs_init(void)
1071{ 1071{
1072#ifdef CONFIG_CPU_MIPSR2_SRS
1073 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1072 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1074 printk(KERN_INFO "%d MIPSR2 register sets available\n", 1073 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1075 shadow_registers.sr_supported); 1074 shadow_registers.sr_supported);
1076#endif
1077 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1075 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1078} 1076}
1079 1077
@@ -1198,7 +1196,14 @@ void *set_vi_handler(int n, void *addr)
1198{ 1196{
1199 return set_vi_srs_handler(n, addr, 0); 1197 return set_vi_srs_handler(n, addr, 0);
1200} 1198}
1201#endif 1199
1200#else
1201
1202static inline void mips_srs_init(void)
1203{
1204}
1205
1206#endif /* CONFIG_CPU_MIPSR2_SRS */
1202 1207
1203/* 1208/*
1204 * This is used by native signal handling 1209 * This is used by native signal handling
@@ -1388,9 +1393,7 @@ void __init trap_init(void)
1388 else 1393 else
1389 ebase = CAC_BASE; 1394 ebase = CAC_BASE;
1390 1395
1391#ifdef CONFIG_CPU_MIPSR2
1392 mips_srs_init(); 1396 mips_srs_init();
1393#endif
1394 1397
1395 per_cpu_trap_init(); 1398 per_cpu_trap_init();
1396 1399