aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/kernel/traps.c
diff options
context:
space:
mode:
authorDavid Daney <ddaney@caviumnetworks.com>2008-10-23 20:56:35 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-10-30 10:44:33 -0400
commit566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e (patch)
tree4f6c7d97bae81c7ce48daaa6c0ce55ef72fb5561 /arch/mips/kernel/traps.c
parent4816227b54d2366cba785e6f3b9f81495b83a5f1 (diff)
MIPS: Consider value of c0_ebase when computing value of exception base.
It just so happens to be zero on all currently supported systems so this hasn't bitten yet ... [Ralf: Original patch from Cavium; handling of set_uncached_handler() and de-ifdef'ed trap_init() implementation by me.] Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r--arch/mips/kernel/traps.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 80b9e070c207..3f6de76d485d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1555,6 +1555,8 @@ void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1555#ifdef CONFIG_64BIT 1555#ifdef CONFIG_64BIT
1556 unsigned long uncached_ebase = TO_UNCAC(ebase); 1556 unsigned long uncached_ebase = TO_UNCAC(ebase);
1557#endif 1557#endif
1558 if (cpu_has_mips_r2)
1559 ebase += (read_c0_ebase() & 0x3ffff000);
1558 1560
1559 if (!addr) 1561 if (!addr)
1560 panic(panic_null_cerr); 1562 panic(panic_null_cerr);
@@ -1588,8 +1590,11 @@ void __init trap_init(void)
1588 1590
1589 if (cpu_has_veic || cpu_has_vint) 1591 if (cpu_has_veic || cpu_has_vint)
1590 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); 1592 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1591 else 1593 else {
1592 ebase = CAC_BASE; 1594 ebase = CAC_BASE;
1595 if (cpu_has_mips_r2)
1596 ebase += (read_c0_ebase() & 0x3ffff000);
1597 }
1593 1598
1594 per_cpu_trap_init(); 1599 per_cpu_trap_init();
1595 1600
@@ -1697,11 +1702,11 @@ void __init trap_init(void)
1697 1702
1698 if (cpu_has_vce) 1703 if (cpu_has_vce)
1699 /* Special exception: R4[04]00 uses also the divec space. */ 1704 /* Special exception: R4[04]00 uses also the divec space. */
1700 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100); 1705 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1701 else if (cpu_has_4kex) 1706 else if (cpu_has_4kex)
1702 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80); 1707 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1703 else 1708 else
1704 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80); 1709 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1705 1710
1706 signal_init(); 1711 signal_init();
1707#ifdef CONFIG_MIPS32_COMPAT 1712#ifdef CONFIG_MIPS32_COMPAT