diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2006-07-08 06:32:58 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2006-07-13 16:26:15 -0400 |
commit | 4bf42d4272d83b42e1492215a34d42dae8e6fccc (patch) | |
tree | bcaf165fc18e7c6bc97d1f9ad6b2bf5959dca570 /arch/mips/kernel/smtc.c | |
parent | 783b09dc2806429560d0211564a94d6570b96ee3 (diff) |
[MIPS] SMTC: Reformat to Linux style.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/smtc.c')
-rw-r--r-- | arch/mips/kernel/smtc.c | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index a48d9e553083..5b17a3d6ae4f 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c | |||
@@ -127,7 +127,7 @@ static int __init stlb_disable(char *s) | |||
127 | static int __init asidmask_set(char *str) | 127 | static int __init asidmask_set(char *str) |
128 | { | 128 | { |
129 | get_option(&str, &asidmask); | 129 | get_option(&str, &asidmask); |
130 | switch(asidmask) { | 130 | switch (asidmask) { |
131 | case 0x1: | 131 | case 0x1: |
132 | case 0x3: | 132 | case 0x3: |
133 | case 0x7: | 133 | case 0x7: |
@@ -249,7 +249,7 @@ void smtc_configure_tlb(void) | |||
249 | /* | 249 | /* |
250 | * Only count if the MMU Type indicated is TLB | 250 | * Only count if the MMU Type indicated is TLB |
251 | */ | 251 | */ |
252 | if(((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { | 252 | if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { |
253 | config1val = read_vpe_c0_config1(); | 253 | config1val = read_vpe_c0_config1(); |
254 | tlbsiz += ((config1val >> 25) & 0x3f) + 1; | 254 | tlbsiz += ((config1val >> 25) & 0x3f) + 1; |
255 | } | 255 | } |
@@ -500,7 +500,7 @@ void mipsmt_prepare_cpus(void) | |||
500 | /* Set up coprocessor affinity CPU mask(s) */ | 500 | /* Set up coprocessor affinity CPU mask(s) */ |
501 | 501 | ||
502 | for (tc = 0; tc < ntc; tc++) { | 502 | for (tc = 0; tc < ntc; tc++) { |
503 | if(cpu_data[tc].options & MIPS_CPU_FPU) | 503 | if (cpu_data[tc].options & MIPS_CPU_FPU) |
504 | cpu_set(tc, mt_fpu_cpumask); | 504 | cpu_set(tc, mt_fpu_cpumask); |
505 | } | 505 | } |
506 | 506 | ||
@@ -582,8 +582,8 @@ void smtc_init_secondary(void) | |||
582 | * SMTC init code assigns TCs consdecutively and in ascending order | 582 | * SMTC init code assigns TCs consdecutively and in ascending order |
583 | * to across available VPEs. | 583 | * to across available VPEs. |
584 | */ | 584 | */ |
585 | if(((read_c0_tcbind() & TCBIND_CURTC) != 0) | 585 | if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && |
586 | && ((read_c0_tcbind() & TCBIND_CURVPE) | 586 | ((read_c0_tcbind() & TCBIND_CURVPE) |
587 | != cpu_data[smp_processor_id() - 1].vpe_id)){ | 587 | != cpu_data[smp_processor_id() - 1].vpe_id)){ |
588 | write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); | 588 | write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); |
589 | } | 589 | } |
@@ -757,8 +757,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) | |||
757 | write_tc_c0_tchalt(0); | 757 | write_tc_c0_tchalt(0); |
758 | UNLOCK_CORE_PRA(); | 758 | UNLOCK_CORE_PRA(); |
759 | /* Try to reduce redundant timer interrupt messages */ | 759 | /* Try to reduce redundant timer interrupt messages */ |
760 | if(type == SMTC_CLOCK_TICK) { | 760 | if (type == SMTC_CLOCK_TICK) { |
761 | if(atomic_postincrement(&ipi_timer_latch[cpu])!=0) { | 761 | if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){ |
762 | smtc_ipi_nq(&freeIPIq, pipi); | 762 | smtc_ipi_nq(&freeIPIq, pipi); |
763 | return; | 763 | return; |
764 | } | 764 | } |
@@ -797,7 +797,7 @@ void post_direct_ipi(int cpu, struct smtc_ipi *pipi) | |||
797 | * CU bit of Status is indicator that TC was | 797 | * CU bit of Status is indicator that TC was |
798 | * already running on a kernel stack... | 798 | * already running on a kernel stack... |
799 | */ | 799 | */ |
800 | if(tcstatus & ST0_CU0) { | 800 | if (tcstatus & ST0_CU0) { |
801 | /* Note that this "- 1" is pointer arithmetic */ | 801 | /* Note that this "- 1" is pointer arithmetic */ |
802 | kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; | 802 | kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1; |
803 | } else { | 803 | } else { |
@@ -840,31 +840,31 @@ void ipi_decode(struct pt_regs *regs, struct smtc_ipi *pipi) | |||
840 | 840 | ||
841 | smtc_ipi_nq(&freeIPIq, pipi); | 841 | smtc_ipi_nq(&freeIPIq, pipi); |
842 | switch (type_copy) { | 842 | switch (type_copy) { |
843 | case SMTC_CLOCK_TICK: | 843 | case SMTC_CLOCK_TICK: |
844 | /* Invoke Clock "Interrupt" */ | 844 | /* Invoke Clock "Interrupt" */ |
845 | ipi_timer_latch[dest_copy] = 0; | 845 | ipi_timer_latch[dest_copy] = 0; |
846 | #ifdef SMTC_IDLE_HOOK_DEBUG | 846 | #ifdef SMTC_IDLE_HOOK_DEBUG |
847 | clock_hang_reported[dest_copy] = 0; | 847 | clock_hang_reported[dest_copy] = 0; |
848 | #endif /* SMTC_IDLE_HOOK_DEBUG */ | 848 | #endif /* SMTC_IDLE_HOOK_DEBUG */ |
849 | local_timer_interrupt(0, NULL, regs); | 849 | local_timer_interrupt(0, NULL, regs); |
850 | break; | ||
851 | case LINUX_SMP_IPI: | ||
852 | switch ((int)arg_copy) { | ||
853 | case SMP_RESCHEDULE_YOURSELF: | ||
854 | ipi_resched_interrupt(regs); | ||
850 | break; | 855 | break; |
851 | case LINUX_SMP_IPI: | 856 | case SMP_CALL_FUNCTION: |
852 | switch ((int)arg_copy) { | 857 | ipi_call_interrupt(regs); |
853 | case SMP_RESCHEDULE_YOURSELF: | ||
854 | ipi_resched_interrupt(regs); | ||
855 | break; | ||
856 | case SMP_CALL_FUNCTION: | ||
857 | ipi_call_interrupt(regs); | ||
858 | break; | ||
859 | default: | ||
860 | printk("Impossible SMTC IPI Argument 0x%x\n", | ||
861 | (int)arg_copy); | ||
862 | break; | ||
863 | } | ||
864 | break; | 858 | break; |
865 | default: | 859 | default: |
866 | printk("Impossible SMTC IPI Type 0x%x\n", type_copy); | 860 | printk("Impossible SMTC IPI Argument 0x%x\n", |
861 | (int)arg_copy); | ||
867 | break; | 862 | break; |
863 | } | ||
864 | break; | ||
865 | default: | ||
866 | printk("Impossible SMTC IPI Type 0x%x\n", type_copy); | ||
867 | break; | ||
868 | } | 868 | } |
869 | } | 869 | } |
870 | 870 | ||
@@ -879,7 +879,7 @@ void deferred_smtc_ipi(struct pt_regs *regs) | |||
879 | * Test is not atomic, but much faster than a dequeue, | 879 | * Test is not atomic, but much faster than a dequeue, |
880 | * and the vast majority of invocations will have a null queue. | 880 | * and the vast majority of invocations will have a null queue. |
881 | */ | 881 | */ |
882 | if(IPIQ[q].head != NULL) { | 882 | if (IPIQ[q].head != NULL) { |
883 | while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) { | 883 | while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) { |
884 | /* ipi_decode() should be called with interrupts off */ | 884 | /* ipi_decode() should be called with interrupts off */ |
885 | local_irq_save(flags); | 885 | local_irq_save(flags); |
@@ -1254,7 +1254,7 @@ void smtc_flush_tlb_asid(unsigned long asid) | |||
1254 | tlb_read(); | 1254 | tlb_read(); |
1255 | ehb(); | 1255 | ehb(); |
1256 | ehi = read_c0_entryhi(); | 1256 | ehi = read_c0_entryhi(); |
1257 | if((ehi & ASID_MASK) == asid) { | 1257 | if ((ehi & ASID_MASK) == asid) { |
1258 | /* | 1258 | /* |
1259 | * Invalidate only entries with specified ASID, | 1259 | * Invalidate only entries with specified ASID, |
1260 | * makiing sure all entries differ. | 1260 | * makiing sure all entries differ. |