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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 16:44:45 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-29 16:44:45 -0400
commit8d231c11fd0b694c447e59e687754b6999eea0a2 (patch)
treeb0b3c17efff7018bbf948e489f642c8079f33cc0 /arch/mips/kernel/smtc-asm.S
parent1f1332f727c3229eb2166a83fec5d3de6a73dce2 (diff)
parent8db089c6b5594c961fb6bc6d613b9926e0d3d98f (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (33 commits) [MIPS] Add missing backslashes to macro definitions. [MIPS] Death list of board support to be removed after 2.6.18. [MIPS] Remove BSD and Sys V compat data types. [MIPS] ioc3.h: Uses u8, so include <linux/types.h>. [MIPS] 74K: Assume it will also have an AR bit in config7 [MIPS] Treat CPUs with AR bit as physically indexed. [MIPS] Oprofile: Support VSMP on 34K. [MIPS] MIPS32/MIPS64 S-cache fix and cleanup [MIPS] excite: PCI makefile needs to use += if it wants a chance to work. [MIPS] excite: plat_setup -> plat_mem_setup. [MIPS] au1xxx: export dbdma functions [MIPS] au1xxx: dbdma, no sleeping under spin_lock [MIPS] au1xxx: fix PSC_SMBTXRX_RSR. [MIPS] Early printk for IP27. [MIPS] Fix handling of 0 length I & D caches. [MIPS] Typo fixes. [MIPS] MIPS32/MIPS64 secondary cache management [MIPS] Fix FIXADDR_TOP for TX39/TX49. [MIPS] Remove first timer interrupt setup in wrppmc_timer_setup() [MIPS] Fix configuration of R2 CPU features and multithreading. ...
Diffstat (limited to 'arch/mips/kernel/smtc-asm.S')
-rw-r--r--arch/mips/kernel/smtc-asm.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index c9d65196d917..72c6d98f8854 100644
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -52,12 +52,12 @@ FEXPORT(__smtc_ipi_vector)
52 .set noat 52 .set noat
53 /* Disable thread scheduling to make Status update atomic */ 53 /* Disable thread scheduling to make Status update atomic */
54 DMT 27 # dmt k1 54 DMT 27 # dmt k1
55 ehb 55 _ehb
56 /* Set EXL */ 56 /* Set EXL */
57 mfc0 k0,CP0_STATUS 57 mfc0 k0,CP0_STATUS
58 ori k0,k0,ST0_EXL 58 ori k0,k0,ST0_EXL
59 mtc0 k0,CP0_STATUS 59 mtc0 k0,CP0_STATUS
60 ehb 60 _ehb
61 /* Thread scheduling now inhibited by EXL. Restore TE state. */ 61 /* Thread scheduling now inhibited by EXL. Restore TE state. */
62 andi k1,k1,VPECONTROL_TE 62 andi k1,k1,VPECONTROL_TE
63 beqz k1,1f 63 beqz k1,1f
@@ -82,7 +82,7 @@ FEXPORT(__smtc_ipi_vector)
82 li k1,ST0_CU0 82 li k1,ST0_CU0
83 or k1,k1,k0 83 or k1,k1,k0
84 mtc0 k1,CP0_STATUS 84 mtc0 k1,CP0_STATUS
85 ehb 85 _ehb
86 get_saved_sp 86 get_saved_sp
87 /* Interrupting TC will have pre-set values in slots in the new frame */ 87 /* Interrupting TC will have pre-set values in slots in the new frame */
882: subu k1,k1,PT_SIZE 882: subu k1,k1,PT_SIZE
@@ -90,7 +90,7 @@ FEXPORT(__smtc_ipi_vector)
90 lw k0,PT_TCSTATUS(k1) 90 lw k0,PT_TCSTATUS(k1)
91 /* Write it to TCStatus to restore CU/KSU/IXMT state */ 91 /* Write it to TCStatus to restore CU/KSU/IXMT state */
92 mtc0 k0,$2,1 92 mtc0 k0,$2,1
93 ehb 93 _ehb
94 lw k0,PT_EPC(k1) 94 lw k0,PT_EPC(k1)
95 mtc0 k0,CP0_EPC 95 mtc0 k0,CP0_EPC
96 /* Save all will redundantly recompute the SP, but use it for now */ 96 /* Save all will redundantly recompute the SP, but use it for now */
@@ -116,7 +116,7 @@ LEAF(self_ipi)
116 mfc0 t0,CP0_TCSTATUS 116 mfc0 t0,CP0_TCSTATUS
117 ori t1,t0,TCSTATUS_IXMT 117 ori t1,t0,TCSTATUS_IXMT
118 mtc0 t1,CP0_TCSTATUS 118 mtc0 t1,CP0_TCSTATUS
119 ehb 119 _ehb
120 /* We know we're in kernel mode, so prepare stack frame */ 120 /* We know we're in kernel mode, so prepare stack frame */
121 subu t1,sp,PT_SIZE 121 subu t1,sp,PT_SIZE
122 sw ra,PT_EPC(t1) 122 sw ra,PT_EPC(t1)