diff options
| author | Steve French <sfrench@us.ibm.com> | 2006-03-03 06:27:25 -0500 |
|---|---|---|
| committer | Steve French <sfrench@us.ibm.com> | 2006-03-03 06:27:25 -0500 |
| commit | c6ee60b7c8bbc78e3b1776b2820a7e7f95f8996a (patch) | |
| tree | 99b48ef0f5217fddc0aa897d9e60d95ace7da6ff /arch/mips/kernel/smp_mt.c | |
| parent | 13298defe5323c7fdcac268f588d8d1090758fb8 (diff) | |
| parent | c499ec24c31edf270e777a868ffd0daddcfe7ebd (diff) | |
Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Signed-off-by: Steve French <sfrench@us.ibm.com>
Diffstat (limited to 'arch/mips/kernel/smp_mt.c')
| -rw-r--r-- | arch/mips/kernel/smp_mt.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/mips/kernel/smp_mt.c b/arch/mips/kernel/smp_mt.c index c930364830d0..993b8bf56aaf 100644 --- a/arch/mips/kernel/smp_mt.c +++ b/arch/mips/kernel/smp_mt.c | |||
| @@ -143,7 +143,7 @@ static struct irqaction irq_call = { | |||
| 143 | * Make sure all CPU's are in a sensible state before we boot any of the | 143 | * Make sure all CPU's are in a sensible state before we boot any of the |
| 144 | * secondarys | 144 | * secondarys |
| 145 | */ | 145 | */ |
| 146 | void prom_prepare_cpus(unsigned int max_cpus) | 146 | void plat_smp_setup(void) |
| 147 | { | 147 | { |
| 148 | unsigned long val; | 148 | unsigned long val; |
| 149 | int i, num; | 149 | int i, num; |
| @@ -179,11 +179,9 @@ void prom_prepare_cpus(unsigned int max_cpus) | |||
| 179 | write_vpe_c0_vpeconf0(tmp); | 179 | write_vpe_c0_vpeconf0(tmp); |
| 180 | 180 | ||
| 181 | /* Record this as available CPU */ | 181 | /* Record this as available CPU */ |
| 182 | if (i < max_cpus) { | 182 | cpu_set(i, phys_cpu_present_map); |
| 183 | cpu_set(i, phys_cpu_present_map); | 183 | __cpu_number_map[i] = ++num; |
| 184 | __cpu_number_map[i] = ++num; | 184 | __cpu_logical_map[num] = i; |
| 185 | __cpu_logical_map[num] = i; | ||
| 186 | } | ||
| 187 | } | 185 | } |
| 188 | 186 | ||
| 189 | /* disable multi-threading with TC's */ | 187 | /* disable multi-threading with TC's */ |
| @@ -241,7 +239,10 @@ void prom_prepare_cpus(unsigned int max_cpus) | |||
| 241 | set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); | 239 | set_vi_handler (MIPS_CPU_IPI_RESCHED_IRQ, ipi_resched_dispatch); |
| 242 | set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); | 240 | set_vi_handler (MIPS_CPU_IPI_CALL_IRQ, ipi_call_dispatch); |
| 243 | } | 241 | } |
| 242 | } | ||
| 244 | 243 | ||
| 244 | void __init plat_prepare_cpus(unsigned int max_cpus) | ||
| 245 | { | ||
| 245 | cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; | 246 | cpu_ipi_resched_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_RESCHED_IRQ; |
| 246 | cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; | 247 | cpu_ipi_call_irq = MIPSCPU_INT_BASE + MIPS_CPU_IPI_CALL_IRQ; |
| 247 | 248 | ||
