diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2014-05-23 10:29:44 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-23 18:07:01 -0400 |
commit | b633648c5ad3cfbda0b3daea50d2135d44899259 (patch) | |
tree | 6100185cae10f36a55e71c3b220fc79cfa14b7c0 /arch/mips/kernel/smp.c | |
parent | 8b2e62cc34feaaf1cac9440a93fb18ac0b1e81bc (diff) |
MIPS: MT: Remove SMTC support
Nobody is maintaining SMTC anymore and there also seems to be no userbase.
Which is a pity - the SMTC technology primarily developed by Kevin D.
Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT
ASE's power and elegance.
Based on Markos Chandras <Markos.Chandras@imgtec.com> patch
https://patchwork.linux-mips.org/patch/6719/ which while very similar did
no longer apply cleanly when I tried to merge it plus some additional
post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to
merge once upon a time.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/smp.c')
-rw-r--r-- | arch/mips/kernel/smp.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 0a022ee33b2a..35bb05a13f05 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c | |||
@@ -43,10 +43,6 @@ | |||
43 | #include <asm/time.h> | 43 | #include <asm/time.h> |
44 | #include <asm/setup.h> | 44 | #include <asm/setup.h> |
45 | 45 | ||
46 | #ifdef CONFIG_MIPS_MT_SMTC | ||
47 | #include <asm/mipsmtregs.h> | ||
48 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
49 | |||
50 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ | 46 | volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ |
51 | 47 | ||
52 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ | 48 | int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ |
@@ -102,12 +98,6 @@ asmlinkage void start_secondary(void) | |||
102 | { | 98 | { |
103 | unsigned int cpu; | 99 | unsigned int cpu; |
104 | 100 | ||
105 | #ifdef CONFIG_MIPS_MT_SMTC | ||
106 | /* Only do cpu_probe for first TC of CPU */ | ||
107 | if ((read_c0_tcbind() & TCBIND_CURTC) != 0) | ||
108 | __cpu_name[smp_processor_id()] = __cpu_name[0]; | ||
109 | else | ||
110 | #endif /* CONFIG_MIPS_MT_SMTC */ | ||
111 | cpu_probe(); | 101 | cpu_probe(); |
112 | cpu_report(); | 102 | cpu_report(); |
113 | per_cpu_trap_init(false); | 103 | per_cpu_trap_init(false); |
@@ -238,13 +228,10 @@ static void flush_tlb_mm_ipi(void *mm) | |||
238 | * o collapses to normal function call on UP kernels | 228 | * o collapses to normal function call on UP kernels |
239 | * o collapses to normal function call on systems with a single shared | 229 | * o collapses to normal function call on systems with a single shared |
240 | * primary cache. | 230 | * primary cache. |
241 | * o CONFIG_MIPS_MT_SMTC currently implies there is only one physical core. | ||
242 | */ | 231 | */ |
243 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) | 232 | static inline void smp_on_other_tlbs(void (*func) (void *info), void *info) |
244 | { | 233 | { |
245 | #ifndef CONFIG_MIPS_MT_SMTC | ||
246 | smp_call_function(func, info, 1); | 234 | smp_call_function(func, info, 1); |
247 | #endif | ||
248 | } | 235 | } |
249 | 236 | ||
250 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) | 237 | static inline void smp_on_each_tlb(void (*func) (void *info), void *info) |