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authorDouglas Leung <douglas@mips.com>2012-07-19 03:11:13 -0400
committerRalf Baechle <ralf@linux-mips.org>2012-07-19 05:23:43 -0400
commitdc34b05fea0cc9a869863b929f37f1e8ce30edf4 (patch)
treead064e7dcf5235d8c51060ed0c8db167c5490bd3 /arch/mips/kernel/r4k_switch.S
parentc022630633624a75b3b58f43dd3c6cc896a56cff (diff)
MIPS: Fix decoding of c0_config1 for MIPSxx caches with 32 ways per set.
This affects certain 4Kc cores. Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Steven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3855/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/r4k_switch.S')
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