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authorRalf Baechle <ralf@linux-mips.org>2005-09-03 18:56:16 -0400
committerLinus Torvalds <torvalds@evo.osdl.org>2005-09-05 03:06:06 -0400
commit875d43e72b5bf22161a81de7554f88eccf8a51ae (patch)
treea676fe7298b478b7ee9fe7be9cb07c9a0b928370 /arch/mips/kernel/r4k_fpu.S
parent63fb6fd1c86181d9dd9ba0e6e6082799e149b56b (diff)
[PATCH] mips: clean up 32/64-bit configuration
Start cleaning 32-bit vs. 64-bit configuration. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/mips/kernel/r4k_fpu.S')
-rw-r--r--arch/mips/kernel/r4k_fpu.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S
index ebb643d8d14c..aba665bcb386 100644
--- a/arch/mips/kernel/r4k_fpu.S
+++ b/arch/mips/kernel/r4k_fpu.S
@@ -36,7 +36,7 @@
36LEAF(_save_fp_context) 36LEAF(_save_fp_context)
37 cfc1 t1, fcr31 37 cfc1 t1, fcr31
38 38
39#ifdef CONFIG_MIPS64 39#ifdef CONFIG_64BIT
40 /* Store the 16 odd double precision registers */ 40 /* Store the 16 odd double precision registers */
41 EX sdc1 $f1, SC_FPREGS+8(a0) 41 EX sdc1 $f1, SC_FPREGS+8(a0)
42 EX sdc1 $f3, SC_FPREGS+24(a0) 42 EX sdc1 $f3, SC_FPREGS+24(a0)
@@ -118,7 +118,7 @@ LEAF(_save_fp_context32)
118 */ 118 */
119LEAF(_restore_fp_context) 119LEAF(_restore_fp_context)
120 EX lw t0, SC_FPC_CSR(a0) 120 EX lw t0, SC_FPC_CSR(a0)
121#ifdef CONFIG_MIPS64 121#ifdef CONFIG_64BIT
122 EX ldc1 $f1, SC_FPREGS+8(a0) 122 EX ldc1 $f1, SC_FPREGS+8(a0)
123 EX ldc1 $f3, SC_FPREGS+24(a0) 123 EX ldc1 $f3, SC_FPREGS+24(a0)
124 EX ldc1 $f5, SC_FPREGS+40(a0) 124 EX ldc1 $f5, SC_FPREGS+40(a0)